专利名称:Information processing apparatus, data
reception device and method of controllingthe information processing apparatus
发明人:Hiroshi Nakayama,Junji Ichimiya,Shintaro
Itozawa
申请号:US129573申请日:20101129公开号:US08516291B2公开日:20130820
专利附图:
摘要:A clock adjustment circuit delays a phase of a clock signal on the basis of a TAP
value so as to output an adjusted clock signal. By synchronizing transmission data withthe adjusted clock signal, reception data is generated. A data adjustment circuit delaysthe transmission data on the basis of a TAP2 value. By synchronizing the delayedtransmission data with the adjusted clock signal, adjusted reception data is generated. Adata adjustment control circuit generates the TAP2 value on the basis of a result of acomparison between the reception data and the adjusted reception data, and outputs toa clock adjustment control circuit an instruction to update the TAP value.
申请人:Hiroshi Nakayama,Junji Ichimiya,Shintaro Itozawa
地址:Kawasaki JP,Kawasaki JP,Kawasaki JP
国籍:JP,JP,JP
代理机构:Staas & Halsey LLP
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