Freescale SemiconductorData Sheet
MPC5200Rev. 4, 01/2005
MPC5200 Data Sheet
NOTE
The information in this document is subject to change. For the latest data on the MPC5200, visit www.freescale.com and proceed to the MPC5200 Product Summary Page.
Table of Contents
123
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Electrical and Thermal Characteristics. . . . . . . . . 63.1DC Electrical Characteristics. . . . . . . . . . . . . 63.2Oscillator and PLL Electrical
Characteristics. . . . . . . . . . . . . . . . . . . . . . . 123.3AC Electrical Characteristics. . . . . . . . . . . . 14Package Description. . . . . . . . . . . . . . . . . . . . . . 4.1Package Parameters. . . . . . . . . . . . . . . . . . 4.2Mechanical Dimensions. . . . . . . . . . . . . . . . 4.3Pinout Listings. . . . . . . . . . . . . . . . . . . . . . . 66System Design Information. . . . . . . . . . . . . . . . . 715.1Power UP/Down Sequencing . . . . . . . . . . . 715.2System and CPU Core AVDD power
supply filtering . . . . . . . . . . . . . . . . . . . . . . . 735.3Pull-up/Pull-down Resistor Requirements. . 735.4JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74Ordering Information. . . . . . . . . . . . . . . . . . . . . . 79Document Revision History. . . . . . . . . . . . . . . . . 79
4
1Overview
5
The MPC5200 integrates a high performance MPC603e series G2_LE core with a rich set of peripheral functions focused on communications and systems integration. The G2_LE core design is based on the PowerPCTM core architecture. MPC5200 incorporates an innovative BestComm I/O subsystem, which isolates routine
maintenance of peripheral functions from the embedded G2_LE core. The MPC5200 contains a SDRAM/DDR Memory Controller, a flexible External Bus Interface, PCI Controller, USB, ATA, Ethernet, six Programmable Serial Controllers (PSC), I2C, SPI, CAN, J1850, Timers, and GPIOs.
67
“Definitive Data: Freescale reserves the right to change the production detail specificationsas may be required to permit improvements in the design of its products.”©Freescale Semiconductor, Inc., 2005, 2006. All rights reserved.
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Features
2Features
Key features are shown below.
•MPC603e series G2_LE core—Superscalar architecture
—760 MIPS at 400 MHz (-40 to +85 oC)—16 k Instruction cache, 16 k Data cache—Double precision FPU—Instruction and Data MMU
—Standard and Critical interrupt capability•SDRAM / DDR Memory Interface—up to 132-MHz operation
—SDRAM and DDR SDRAM support
—256-MByte addressing range per CS, two CS available—32-bit data bus
—Built-in initialization and refresh
•Flexible multi-function External Bus Interface
—Supports interfacing to ROM/Flash/SRAM memories or other memory mapped devices—8 programmable Chip Selects
—Non multiplexed data access using 8/16/32 bit databus with up to 26-bit address—Short or Long Burst capable
—Multiplexed data access using 8/16/32 bit databus with up to 25-bit address•Peripheral Component Interconnect (PCI) Controller
—Version 2.2 PCI compatibility—PCI initiator and target operation—32-bit PCI Address/Data bus —33- and 66-MHz operation—PCI arbitration function•ATA Controller
—Version 4 ATA compatible external interface—IDE Disk Drive connectivity•BestComm DMA subsystem
—Intelligent virtual DMA Controller
—Dedicated DMA channels to control peripheral reception and transmission—Local memory (SRAM 16 kBytes)
•6 Programmable Serial Controllers (PSC), configurable for the following:
—UART or RS232 interface
MPC5200 Data Sheet, Rev. 4
2
Freescale Semiconductor
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Features
••
•••
•
•
—CODEC interface for Soft Modem, Master/Slave CODEC Mode, I2S and AC97—Full duplex SPI mode
—IrDA mode from 2400 bps to 4 MbpsFast Ethernet Controller (FEC)
—Supports 100Mbps IEEE 802.3 MII, 10 Mbps IEEE 802.3 MII, 10 Mbps 7-wire interfaceUniversal Serial Bus Controller (USB) —USB Revision 1.1 Host
—Open Host Controller Interface (OHCI)—Integrated USB Hub, with two ports.Two Inter-Integrated Circuit Interfaces (I2C)Serial Peripheral Interface (SPI)
Dual CAN 2.0 A/B Controller (MSCAN)
—Freescale Scalable Controller Area Network (FSCAN) architecture—Implementation of version 2.0A/B CAN protocol—Standard and extended data framesJ1850 Byte Data Link Controller (BDLC)
—J1850 Class B data communication network interface compatible and ISO compatible for low
speed (<125 kbps) serial data communications in automotive applications.—Supports 4X mode, 41.6 kbps
—In-frame response (IFR) types 0, 1, 2, and 3 supportedSystems level features
—Interrupt Controller supports four external interrupt request lines and 47 internal interrupt
sources
—GPIO/Timer functions
–Up to 56 total GPIO pins (depending on functional multiplexing selections) that support a variety of interrupt/WakeUp capabilities.
–Eight GPIO pins with timer capability supporting input capture, output compare, and pulse width modulation (PWM) functions
—Real-time Clock with one-second resolution
—Systems Protection (watch dog timer, bus monitor)—Individual control of functional block clock sources
—Power management: Nap, Doze, Sleep, Deep Sleep modes
—Support of WakeUp from low power modes by different sources (GPIO, RTC, CAN)
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor
3
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Features
•
•
Test/Debug features
—JTAG (IEEE 1149.1 test access port)
—Common On-chip Processor (COP) debug portOn-board PLL and clock generation
Figure1 shows a simplified MPC5200 block diagram.
MPC5200 Data Sheet, Rev. 4
4
Freescale Semiconductor
SDRAM / DDR元器件交易网www.cecb2b.com
Freescale Semiconductor
Systems Interface Unit (SIU)SDRAM / DDRMemory Controller 603Real-Time ClockSystem FunctionsInterrupt ControllerGPIO/TimersLocal Plus ControllerLocalBusG2_LE CoreJTAG / COPInterfacePCI Bus ControllerBestComm DMASRAM 16KReset / ClockGenerationFigure1. Simplified Block Diagram—MPC5200
ATA Host ControllerMPC5200 Data Sheet, Rev. 4
CommBusSPIUSB2xI2C2xMSCAN2xJ1850EthernetPSC6xFeatures
5
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Electrical and Thermal Characteristics
3
3.1
3.1.1
Electrical and Thermal Characteristics
DC Electrical Characteristics
Absolute Maximum Ratings
Table1. Absolute Maximum Ratings1
Characteristic
Supply voltage - G2_LE core and peripheral logicSupply voltage - I/O buffersSupply voltage - System APLLSupply voltage - G2_LE APLLInput voltage (VDD_IO)Input voltage (VDD_MEM_IO)Input voltage overshoot Input voltage undershoot Storage temperature range
SymbolVDD_COREVDD_IO,VDD_MEM_IOSYS_PLL_AVDDCORE_PLL_AVDD
VinVinVinosVinusTstg
Min–0.3–0.3–0.3–0.3–0.3–0.3–––55
Max1.83.62.12.1VDD_IO + 0.3VDD_MEM_IO
+ 0.3
1.01.0150
UnitVVVVVVVV
oThe tables in this section describe the MPC5200 DC Electrical characteristics. Table 1 gives the absolute maximum ratings.
SpecIDD1.1D1.2D1.3D1.4D1.5D1.6D1.7D1.8D1.9
C
NOTES:
1Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage.
3.1.2Recommended Operating Conditions
Table2. Recommended Operating Conditions
Characteristic
SymbolVDD_COREVDD_IOVDD_MEM_IOSDRVDD_MEM_IODDRSYS_PLL_AVDDCORE_PLL_AVDD
VinVinSDR
Min11.423.03.02.421.421.4200
Max(1)1.583.63.62.631.581.58VDD_IOVDD_MEM_IOSDR
UnitVVVVVVVV
SpecIDD2.1D2.2D2.3D2.4D2.5D2.6D2.7D2.8
Table 2 gives the recommended operating conditions.
Supply voltage - G2_LE core and peripheral logic
Supply voltage - standard I/O buffersSupply voltage - memory I/O buffers (SDR)Supply voltage - memory I/O buffers (DDR)Supply voltage - System APLLSupply voltage - G2_LE APLLInput voltage - standard I/O buffersInput voltage - memory I/O buffers (SDR)
MPC5200 Data Sheet, Rev. 4
6
Freescale Semiconductor
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Electrical and Thermal Characteristics
Table2. Recommended Operating Conditions (continued)
Characteristic
Input voltage - memory I/O buffers (DDR)Ambient operating temperature range2Extended ambient operating temperature range3
Die junction operating temperature rangeExtended die junction operating temperature range
SymbolVinDDRTATAextTjTjext
Min10-40-40-40-40
Max(1)
VDD_MEM_IODDR
+85+105+115+125
UnitV
oCoSpecIDD2.9D2.10D2.11D2.12D2.13
C
oCoC
NOTES:1
These are recommended and tested operating conditions. Proper device operation outside these conditions is not guaranteed.
2Maximum G2_LE core operating frequency is 400 MHz3
Maximum G2_LE core operating frequency is 2 MHz
3.1.3DC Electrical Specifications
Table 3 gives the DC Electrical characteristics for the MPC5200 at recommended operating conditions (see Table 2).
Table3. DC Electrical Specifications
Characteristic
Input high voltageInput high voltageInput high voltageInput high voltageInput high voltageInput high voltageInput low voltageInput low voltageInput low voltageInput low voltageInput low voltageInput low voltage
Condition
Input type = TTL
VDD_IO/VDD_MEM_IOSDR
Input type = TTLVDD_MEM_IODDRInput type = PCI
VDD_IOInput type = SCHMITT
VDD_IO
SYS_XTAL_INRTC_XTAL_INInput type = TTL
VDD_IO/VDD_MEM_IOSDR
Input type = TTLVDD_MEM_IODDRInput type = PCI
VDD_IOInput type = SCHMITT
VDD_IO
SYS_XTAL_INRTC_XTAL_IN
SymbolVIHVIHVIHVIHCVIHCVIHVILVILVILVILCVILCVIL
Min2.01.72.02.02.02.0——————
Max——————0.80.70.80.80.80.8
UnitVVVVVVVVVVVV
SpecIDD3.1D3.2D3.3D3.4D3.5D3.6D3.7D3.8D3.9D3.10D3.11D3.12
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor
7
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Electrical and Thermal Characteristics
Table3. DC Electrical Specifications (continued)
Characteristic
Input leakage current
Condition
Vin = 0 or
VDD_IO/VDD_IO_MEMSDR
1
(depending on input type)
SymbolIIN
Min—
Max+10UnitµA
SpecIDD3.13
Input leakage currentInput leakage currentInput current, pullup resistor
SYS_XTAL_INVin = 0 or VDD_IORTC_XTAL_INVin = 0 or VDD_IO
PULLUPVDD_IOVin = 0PULLUP_MEMVDD_IO_MEMSDR
Vin = 0PULLDOWNVDD_IOVin = VDD_IO
IOH is driver dependent2VDD_IO, VDD_IO_MEMSDRIOH is driver dependent2VDD_IO_MEMDDRIOL is driver dependent2VDD_IO, VDD_IO_MEMSDRIOL is driver dependent2VDD_IO_MEMDDR
IINIINIINpu
——40
+10+10109
µAµAµA
D3.14D3.15D3.16
Input current, pullup resistor - memory I/O buffers
Input current, pulldown resistor
IINpu
41111µAD3.17
IINpd
36106µAD3.18
Output high voltageOutput high voltageOutput low voltageOutput low voltage
DC Injection Current Per Pin3Capacitance
1
VOHVOHDDRVOLVOLDDRICS
2.41.7——-1.0—
——0.40.41.015
VVVVmApF
D3.19D3.20D3.21D3.22D3.23D3.24
Vin = 0V, f = 1 MHz
Cin
NOTES:
Leakage current is measured with output drivers disabled and pull-up/pull-downs inactive.
2See Table 4 for the typical drive capability of a specific signal pin based on the type of output driver associated with that pin as listed in Table 52.
3All injection current is transferred to VDD_IO/VDD_IO_MEM. An external load is required to dissipate this current to maintain the power supply within the specified voltage range.
Total injection current for all digital input-only and all digital input/output pins must not exceed 10 mA. Exceeding this limit can cause disruption of normal operation.
Table4. Drive Capability of MPC5200 Output Pins
Driver TypeDRV4DRV8
Supply VoltageVDD_IO = 3.3VVDD_IO = 3.3V
IOH48
IOL48
UnitmAmA
SpecIDD3.25D3.26
MPC5200 Data Sheet, Rev. 4
8
Freescale Semiconductor
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Electrical and Thermal Characteristics
Table4. Drive Capability of MPC5200 Output Pins (continued)
Driver TypeDRV8_ODDRV16_MEMDRV16_MEMPCI
Supply VoltageVDD_IO = 3.3VVDD_IO_MEM = 3.3VVDD_IO_MEM = 2.5VVDD_IO = 3.3V
IOH-161616
IOL8161616
UnitmAmAmAmA
SpecIDD3.27D3.28D3.29D3.30
3.1.4Electrostatic Discharge
CAUTION
This device contains circuitry that protects against damage due to
high-static voltage or electrical fields. However, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages. Operational reliability is enhanced if unused inputs are tied to an appropriate logic voltage level (i.e., either GND or VCC). Table7 gives package thermal characteristics for this device.
Table5. ESD and Latch-Up Protection Characteristics
SymVHBMVMM
Rating
Human Body Model (HBM)—JEDEC JESD22-A114-BMachine Model (MM)—JEDEC JESD22-A115Latch-up Current at TA=85oCpositivenegative
Latch-up Current at TA=27oCpositivenegative
Min2000200500+100-100+200-200
Max————
UnitVVVmA
SpecIDD4.1D4.2D4.3D4.4
VCDMCharge Device Model (CDM)—JEDEC JESD22-C101ILAT
ILAT
D4.5
—
mA
3.1.5Power Dissipation
Power dissipation of the MPC5200 is caused by 3 different components: the dissipation of the internal or core digital logic (supplied by VDD_CORE), the dissipation of the analog circuitry (supplied by SYS_PLL_AVDD and CORE_PLL_AVDD) and the dissipation of the IO logic (supplied by
VDD_IO_MEM and VDD_IO). Table6 details typical measured core and analog power dissipation figures for a range of operating modes. However, the dissipation due to the switching of the IO pins can not be given in general, but must be calculated by the user for each application case using the following formula
PIO=PIOint+
∑
M
2
N×C×VDD_IO×f
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor
9
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Electrical and Thermal Characteristics
where N is the number of output pins switching in a group M, C is the capacitance per pin, VDD_IO is the IO voltage swing, f is the switching frequency and PIOint is the power consumed by the unloaded IO stage. The total power consumption of the MPC5200 processor must not exceed the value, which would cause the maximum junction temperature to be exceeded.
Ptotal=Pcore+Panalog+PIOTable6. Power Dissipation
Core Power Supply (VDD_CORE)SYS_XTAL/XLB/PCI/IPG/CORE (MHz)
SpecID
Mode
33/66/33/33/2
Typ
OperationalDozeNapSleepDeep-Sleep
727.5———52.5
33/132/66/132/396
Typ108060022522552.5
mWmWmWmWmW
12UnitNotes
,D5.1D5.2D5.3D5.4D5.5
13,
1,415,,
16PLL Power Supplies (SYS_PLL_AVDD, CORE_PLL_AVDD)
ModeTypical
Typ2
Unloaded I/O Power Supplies (VDD_IO, VDD_MEM_IO8)
ModeTypical
Typ33
UnitmW
Notes
9UnitmW
Notes
7D5.6
D5.7
NOTES:
1Typical core power is measured at VDD_CORE = 1.5 V, Tj = 25 C2
Operational power is measured while running an entirely cache-resident program with floating-point multiplication instructions in parallel with a continuous PCI transaction via BestComm.3
Doze power is measured with the G2_LE core in Doze mode, the system oscillator, System PLL and Core PLL are active, all other system modules are inactive4
Nap power is measured with the G2_LE core in Nap mode, the stem oscillator, System PLL and Core PLL are active, all other system modules are inactive5
Sleep power is measured with the G2_LE core in Sleep mode, the stem oscillator, System PLL and Core PLL are active, all other system modules are inactive
6Deep-Sleep power is measured with the G2_LE core in Sleep mode, the stem oscillator, System PLL, Core PLL and all other system modules are inactive7
Typical PLL power is measured at SYS_PLL_AVDD = CORE_PLL_AVDD = 1.5 V, Tj = 25 C
8IO power figures given in the table represent the worst case scenario. For the mem_io rail connected to 2.5V the IO power is expected to be lower and bounded by the worst case with VDD_MEM_IO connected to 3.3V.9Unloaded typical I/O power is measured in Deep-Sleep mode at VDD_IO = VDD_MEM_IO
SDR= 3.3 V, Tj = 25 C
MPC5200 Data Sheet, Rev. 4
10
Freescale Semiconductor
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Electrical and Thermal Characteristics
3.1.6Thermal Characteristics
Table7. Thermal Resistance Data
Rating
Value
Single layer board(1s)
Four layer board (2s2p)
RθJARθJMARθJMARθJMARθJBRθJC
Natural Convection
ΨJT
302224191482
Unit°C/W°C/W°C/W°C/W°C/W°C/W°C/W
Notes
1,2SpecIDD6.1D6.2D6.3D6.4D6.5D6.6D6.7
Junction to Ambient Natural ConvectionJunction to Ambient Natural Convection
1,3Junction to Ambient (@200 Single layer boardft/min)(1s)Junction to Ambient (@200 Four layer boardft/min)(2s2p)Junction to BoardJunction to Case Junction to Package Top
1,31,3456NOTES:
1Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance.
2Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.3
Per JEDEC JESD51-6 with the board horizontal.
4Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package.
5Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1).6
Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.
3.1.7Heat Dissipation
TJ=TA+(RθJA × PD)
Eqn.1
An estimation of the chip-junction temperature, TJ, can be obtained from the following equation:
where:
TA=ambient temperature for the package (°C)RθJA=junction to ambient thermal resistance (°C/W)PD=power dissipation in package (W)
The junction to ambient thermal resistance is an industry standard value, which provides a quick and easy estimation of thermal performance. Unfortunately, there are two values in common usage: the value determined on a single layer board, and the value obtained on a board with two planes. For packages such as the PBGA, these values can be different by a factor of two. Which value is correct depends on the power dissipated by other components on the board. The value obtained on a single layer board is appropriate for the tightly packed printed circuit board. The value obtained on the board with the internal planes is usually appropriate if the board has low power dissipation and the components are well separated.
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor
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Electrical and Thermal Characteristics
Historically, the thermal resistance has frequently been expressed as the sum of a junction to case thermal resistance and a case to ambient thermal resistance:
RθJA=RθJC+RθCA
where:
Eqn.2
RθJA=junction to ambient thermal resistance (°C/W)RθJC=junction to case thermal resistance (°C/W)RθCA=case to ambient thermal resistance (°C/W)
RθJC is device related and cannot be influenced by the user. The user controls the thermal environment to change the case to ambient thermal resistance, RθCA. For instance, the user can change the air flow around the device, add a heat sink, change the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. This description is most useful for ceramic packages with heat sinks where some 90% of the heat flow is through the case to the heat sink to ambient. For most packages, a better model is required.
A more accurate thermal model can be constructed from the junction to board thermal resistance and the junction to case thermal resistance1-3. The junction to case covers the situation where a heat sink will be used or where a substantial amount of heat is dissipated from the top of the package. The junction to board thermal resistance describes the thermal performance when most of the heat is conducted to the printed circuit board. This model can be used for either hand estimations or for a computational fluid dynamics (CFD) thermal model.
To determine the junction temperature of the device in the application after prototypes are available, the Thermal Characterization Parameter (ΨJT) can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using the following equation:
TJ=TT+(ΨJT × PD)
Eqn.3
where:
TT=thermocouple temperature on top of package (°C)ΨJT=thermal characterization parameter (°C/W)PD=power dissipation in package (W)
The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned, so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over approximately one mm of wire extending from the junction. The
thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire.
3.2Oscillator and PLL Electrical Characteristics
The MPC5200 System requires a system-level clock input SYS_XTAL. This clock input may be driven directly from an external oscillator or with a crystal using the internal oscillator.
MPC5200 Data Sheet, Rev. 4
12
Freescale Semiconductor
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Electrical and Thermal Characteristics
There is a separate oscillator for the independent Real-Time Clock (RTC) system. The MPC5200 clock generation uses two phase locked loop (PLL) blocks. •
The system PLL (SYS_PLL) takes an external reference frequency and generates the internal system clock. The system clock frequency is determined by the external reference frequency and the settings of the SYS_PLL configuration.
The G2_LE core PLL (CORE_PLL) generates a master clock for all of the CPU circuitry. The G2_LE core clock frequency is determined by the system clock frequency and the settings of the CORE_PLL configuration.
•
3.2.1System Oscillator Electrical Characteristics
Table8. System Oscillator Electrical Characteristics
Characteristic
Symbolfsys_xtaltup_osc
Notes
Min15.6—
Typical33.3—
Max35.0100
UnitMHzµs
SpecIDO1.1O1.2
SYS_XTAL frequencyOscillator start-up time
3.2.2RTC Oscillator Electrical Characteristics
Table9. RTC Oscillator Electrical Characteristics
Characteristic
Symbolfrtc_xtal
Notes
Min—
Typical32.768
Max—
UnitkHz
SpecIDO2.1
RTC_XTAL frequency
3.2.3System PLL Electrical Characteristics
Table10. System PLL Specifications
Characteristic
Symbolfsys_xtalTsys_xtaltjitterfVCOsystlock
Notes
1(1)2(1)3Min15.666.6—250—
Typical33.330.0—533—
Max35.028.5150800100
UnitMHznspsMHzµs
SpecIDO3.1O3.2O3.3O3.4O3.5
SYS_XTAL frequencySYS_XTAL cycle timeSYS_XTAL clock input jitterSystem VCO frequencySystem PLL relock time
NOTES:
1The SYS_XTAL frequency and PLL Configuration bits must be chosen such that the resulting system frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum operating frequencies.2
This represents total input jitter - short term and long term combined - and is guaranteed by design. Two different types of jitter can exist on the input to core_sysclk, systemic and true random jitter. True random jitter is rejected, but the PLL. Systemic jitter will be passed into and through the PLL to the internal clock circuitry, directly reducing the operating frequency.3
Relock time is guaranteed by design and characterization. PLL-relock time is the maximum amount of time required for the PLL lock after a stable Vdd and core_sysclk are reached during the power-on reset sequence. This specification also applies when the PLL has been disabled and subsequently re-enabled during sleep modes.
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor
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Electrical and Thermal Characteristics
3.2.4G2_LE Core PLL Electrical Characteristics
The internal clocking of the G2_LE core is generated from and synchronized to the system clock by means of a voltage-controlled core PLL.
Table11. G2_LE PLL Specifications
Characteristic
G2_LE frequencyG2_LE cycle timeG2_LE VCO frequencyG2_LE input clock frequencyG2_LE input clock cycle timeG2_LE input clock jitterG2_LE PLL relock time
SymbolfcoretcorefVCOcorefXLB_CLKtXLB_CLKtjittertlock
23Notes
1(1)(1)Min502.800252.73——
Typical———————
Max55040.0120036750.0150100
UnitMHznsMHzMHznspsµs
SpecIDO4.1O4.2O4.3O4.4O4.5O4.6O4.7
NOTES:
1The XLB_CLK frequency and G2_LE PLL Configuration bits must be chosen such that the resulting system
frequencies, CPU (core) frequency, and G2_LE PLL (VCO) frequency do not exceed their respective maximum or minimum operating frequencies.
2This represents total input jitter - short term and long term combined - and is guaranteed by design. Two different types of jitter can exist on the input to core_sysclk, systemic and true random jitter. True random jitter is rejected, but the PLL. Systemic jitter will be passed into and through the PLL to the internal clock circuitry, directly reducing the operating frequency.
3Relock time is guaranteed by design and characterization. PLL-relock time is the maximum amount of time required for the PLL lock after a stable Vdd and core_sysclk are reached during the power-on reset sequence. This specification also applies when the PLL has been disabled and subsequently re-enabled during sleep modes.
3.3
•••••••••
AC Electrical Characteristics
AC Operating Frequency DataClock AC SpecificationsResets
External InterruptsSDRAMPCI
Local Plus BusATAEthernet
••••••••USBSPIMSCANI2CJ1850PSC
GPIOs and Timers
IEEE 1149.1 (JTAG) AC Specifications
Hyperlinks to the indicated timing specification sections are provided below.
AC Test Timing Conditions:
Unless otherwise noted, all test conditions are as follows:
MPC5200 Data Sheet, Rev. 4
14
Freescale Semiconductor
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Electrical and Thermal Characteristics
•••••
TA = -40 to 85 oCTj = -40 to 115 oC
VDD_CORE = 1.42 to 1.58 VVDD_IO = 3.0 to 3.6 VInput conditions:
All Inputs: tr, tf <= 1 nsOutput Loading:All Outputs: 50 pF
3.3.1AC Operating Frequency Data
Table12. Clock Frequencies
Min
123456
G2_LE Processor CoreSDRAM ClockXL Bus ClockIP Bus Clock
PCI / Local Plus Bus ClockPLL Input Range
—————15.6
Max4001331331336635
UnitsMHzMHzMHzMHzMHzMHz
SpecIDA1.1A1.2A1.3A1.4A1.5A1.6
Table 12 provides the operating frequency information for the MPC5200.
3.3.2Clock AC Specifications
tCYCLEtDUTYVM
tDUTYVM
VM
tRISE
CVIH
SYSCLK
tFALL
CVIL
Figure2. Timing Diagram—SYS_XTAL_IN
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor
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Table13. SYS_XTAL_IN Timing
SymtCYCLEtRISEtFALLtDUTYCVIHCVIL
Description
SYS_XTAL_IN cycle time.1SYS_XTAL_IN rise time.SYS_XTAL_IN fall time.
SYS_XTAL_IN duty cycle (measured at VM).2 SYS_XTAL_IN input voltage highSYS_XTAL_IN input voltage low
Min28.6——40.02.0—
Max.15.05.060.0—0.8
Unitsnsnsns%VV
SpecIDA2.1A2.2A2.3A2.4A2.5A2.6
NOTES:
1CAUTION—The SYS_XTAL_IN frequency and system PLL_CFG[0-6] settings must be chosen such that the
resulting system frequencies do not exceed their respective maximum or minimum operating frequencies. See the MPC5200 User Manual [1].2
SYS_XTAL_IN duty cycle is measured at VM.
3.3.3Resets
The MPC5200 has three reset pins: •PORRESET - Power on Reset•HRESET - Hard Reset•SRESET - Software ResetThese signals are asynchronous I/O signals and can be asserted at any time. The input side uses a Schmitt trigger and requires the same input characteristics as other MPC5200 inputs, as specified in the DC Electrical Specifications section. Table 14 specifies the pulse widths of the Reset inputs.
Table14. Reset Pulse Width
NamePORRESETHRESETSRESETDescriptionPower On ResetHardware ResetSoftware Reset
Min Pulse WidthtVDD_stable+tup_osc+tlock
4 clock cycles4 clock cycles
Max Pulse Width
———
Reference ClockSYS_XTAL_INSYS_XTAL_INSYS_XTAL_IN
SpecIDA3.1A3.2A3.3
Notes:
1.For PORRESET the value of the minimum pulse width reflects the power on sequence. If PORRESET is asserted afterwards its minimum pulse width equals the minimum given for HRESET related to the same reference clock.2.The tVDD_stable describes the time which is needed to get all power supplies stable.3.For tlock, refer to the Oscillator/PLL section of this specification for further details.4.For tup_osc, refer to the Oscillator/PLL section of this specification for further details.
5.Following the deassertion of PORRESET, HRESET and SRESET remain low for 4096 reference clock cycles.6.The deassertion of HRESET for at least the minimum pulse width forces the internal resets to be active for an additional 4096 clock cycles.
NOTE
As long as VDD is not stable the HRESET output is not stable. MPC5200 Data Sheet, Rev. 4
16
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Table15. Reset Rise / Fall Timing
Description
PORRESET fall timePORRESET rise timeHRESET fall timeHRESET rise timeSRESET fall timeSRESET rise timeMin——————
Max Unit111111
msmsmsmsmsms
SpecIDA3.4A3.5A3.6A3.7A3.8A3.9
For additional information, see the MPC5200 User Manual [1].
NOTE
Make sure that the PORRESET does not carry any glitches. The MPC5200 has no filter to prevent them from getting into the chip.NOTE
HRESET and SRESET must have a monotonous rise time.3.3.3.1Reset Configuration Word
During reset (HRESET and PORRESET) the Reset Configuration Word is cached in the related Reset Configuration Word Register with each rising edge of the SYS_XTAL signal. If both resets (HRESET and PORRESET) are inactive (high), the contents of this register get locked after two further SYS_XTAL cycles (see Figure3).
4096 clocks
2 clocksSYS_XTALPORRESETHRESET
RST_CFG_WRD
samplesamplesamplesample
samplesamplesamplesample
samplesample
samplesample
LOCK
Figure3. Reset Configuration Word Locking
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor
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NOTE
Beware of changing the values on the pins of the reset configuration word after the deassertion of PORRESET. This may cause problems because it may change the internal clock ratios and so extend the PLL locking process.
3.3.4External Interrupts
The MPC5200 provides three different kinds of external interrupts:•Four IRQ interrupts
•Eight GPIO interrupts with simple interrupt capability (not available in power-down mode)•Eight WakeUp interrupts (special GPIO pins)The propagation of these three kinds of interrupts to the core is shown in the following graphic:
IRQ08 GPIOs8 GPIOsIRQ1IRQ2IRQ3
PIs
88cint
Encodercore_cintcore_int
GPIO StdGPIO WakeUp
int
GrouperEncoder
G2_LE Core
Main InterruptController
Notes:
1. PIs = Programmable Inputs
2. Grouper and Encoder functions imply programmability in software
Figure4. External interrupt scheme
Due to synchronization, prioritization, and mapping of external interrupt sources, the propagation of external interrupts to the core processor is delayed by several IP_CLK clock cycles. The following table specifies the interrupt latencies in IP_CLK cycles. The IP_CLK frequency is programmable in the Clock Distribution Module (see Note Table 16).
Table16. External interrupt latencies
Interrupt Type
Interrupt Requests
Pin NameIRQ0IRQ0IRQ1IRQ2
IRQ3
Clock Cycles
1010101010
Reference Clock
IP_CLKIP_CLKIP_CLKIP_CLKIP_CLK
Core Interruptcritical (cint)normal (int)normal (int)normal (int)normal (int)
SpecIDA4.1A4.2A4.3A4.5A4.6
MPC5200 Data Sheet, Rev. 4
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Table16. External interrupt latencies (continued)
Interrupt Type
Standard GPIO Interrupts
Pin Name
GPIO_PSC3_4GPIO_PSC3_5
Clock Cycles
121212121212121212121212121212
Reference Clock
IP_CLKIP_CLKIP_CLKIP_CLKIP_CLKIP_CLKIP_CLKIP_CLKIP_CLKIP_CLKIP_CLKIP_CLKIP_CLKIP_CLKIP_CLK
Core Interruptnormal (int)normal (int)normal (int)normal (int)normal (int)normal (int)normal (int)normal (int)normal (int)normal (int)normal (int)normal (int)normal (int)normal (int)normal (int)
SpecIDA4.7A4.8A4.9A4.10A4.11A4.12A4.13A4.14A4.15A4.16A4.17A4.18A4.19A4.20A4.21
GPIO_PSC3_8GPIO_USB_9GPIO_ETHI_4GPIO_ETHI_5GPIO_ETHI_6GPIO_ETHI_7
GPIO WakeUp Interrupts
GPIO_PSC1_4GPIO_PSC2_4GPIO_PSC3_9GPIO_ETHI_8GPIO_IRDA_0DGP_IN0DGP_IN1
Notes:
1)The frequency of IP_CLK depends on register settings in Clock Distribution Module. See the MPC5200 User Manual [1]. 2) The interrupt latency descriptions in the table above are related to non competitive, non masked but enabled external interrupt sources. Take care of interrupt prioritization which may increase the latencies.
Since all external interrupt signals are synchronized into the internal processor bus clock domain, each of these signals has to exceed a minimum pulse width of more than one IP_CLK cycle.
Table17. Minimum pulse width for external interrupts to be recognized
Name
All external interrupts (IRQs, GPIOs)
Min Pulse Width> 1 clock cycle
Max Pulse Width
—
Reference Clock
IP_CLK
SpecIDA4.22
NOTES:
1)The frequency of the IP_CLK depends on the register settings in Clock Distribution Module. See the MPC5200 User Manual [1] for further information.
2)If the same interrupt occurs a second time while its interrupt service routine has not cleared the former one, the second interrupt will not be recognized at all.
Besides synchronization, prioritization, and mapping the latency of an external interrupt to the start of its associated interrupt service routine also depends on the following conditions: To get a minimum interrupt service response time, it is recommended to enable the instruction cache and set up the maximum core clock, XL bus, and IP bus frequencies (depending on board design and programming). In addition, it is advisable to execute an interrupt handler, which has been implemented in assembly code.
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor
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3.3.5
3.3.5.1
Symtmem_clktvalidtholdDMvalidDMhold
SDRAM
Memory Interface Timing-Standard SDRAM Read Command
Table18. Standard SDRAM Memory Read Timing
Description
MEM_CLK period
Control Signals, Address and MBA Valid after rising edge of MEM_CLK
Control Signals, Address and MBA Hold after rising edge of MEM_CLK
DQM valid after rising edge of MEM_CLKDQM hold after rising edge of MEM_CLK
Min7.5—tmem_clk*0.5
—
tmem_clk*0.25-0.7
—0.2
Max—
tmem_clk*0.5+0.4
—
tmem_clk*0.25+0.4
—0.3—
Unitsnsnsnsnsnsnsns
SpecIDA5.1A5.2A5.3A5.4A5.5A5.6A5.7
datasetupMDQ setup to rising edge of MEM_CLKdatahold
MDQ hold after rising edge of MEM_CLK
MEM_CLK
tvalid
thold
Control SignalsActiveNOPREADNOP
DMhold
NOPNOPNOPNOP
DMvalid
DQM (Data Mask)
datasetup
datahold
MDQ (Data)
tvalid
thold
MA (Address)
tvalid
Row
thold
Column
MBA (Bank Selects)
NOTE: Control Signals are composed of RAS, CAS, MEM_WE, MEM_CS, MEM_CS1 and CLK_EN
Figure5. Timing Diagram—Standard SDRAM Memory Read Timing
3.3.5.2Memory Interface Timing-Standard SDRAM Write Command
In Standard SDRAM, all signals are activated on the Mem_clk from the Memory Controller and captured on the Mem_clk clock at the memory device.
MPC5200 Data Sheet, Rev. 4
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Table19. Standard SDRAM Write Timing
Symtmem_clktvalidtholdDMvalidDMholddatavaliddatahold
Description
MEM_CLK period
Control Signals, Address and MBA Valid after rising edge of MEM_CLK
Control Signals, Address and MBA Hold after rising edge of MEM_CLK
DQM valid after rising edge of MEM_CLKDQM hold after rising edge of Mem_clkMDQ valid after rising edge of MEM_CLKMDQ hold after rising edge of MEM_CLK
Min7.5—tmem_clk*0.5
—
tmem_clk*0.25-0.7
—
tmem_clk*0.75-0.7
Max—
tmem_clk*0.5+0.4
—
tmem_clk*0.25+0.4
—
tmem_clk*0.75+0.4
—
Unitsnsnsnsnsnsnsns
SpecIDA5.8A5.9A5.10A5.11A5.12A5.13A5.14
MEM_CLK
tvalid
thold
Control SignalsActive
DMvalid
NOPWRITENOP
DMhold
NOPNOPNOPNOP
DQM (Data Mask)
datavalid
datahold
MDQ (Data)
tvalid
thold
MA (Address)
tvalid
Row
thold
Column
MBA (Bank Selects)
NOTE: Control Signals are composed of RAS, CAS, MEM_WE, MEM_CS, MEM_CS1 and CLK_EN
Figure6. Timing Diagram—Standard SDRAM Memory Write Timing
3.3.5.3Memory Interface Timing-DDR SDRAM Read Command
The SDRAM Memory Controller uses an internally skewed clock for reading DDR memory. The
programmable bits in the Reset Configuration Register used to account for unknown board delays are in the CDM module. The internal read clock can be delayed up to 3 ns under worst operating conditions in 32 increments of 95 ps, (1.4 ns in 45 ps increments under best case operating conditions) by programming the CDM Reset Configuration Register tap delay bits. Note: These bits in the CDM Reset Configuration register are not ‘reset configured’ but have a hard coded reset value and are writable during operation.
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor
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Table20. DDR SDRAM Memory Read Timing
Symtmem_clktvalidthold
Description
MEM_CLK period
Control Signals, Address and MBA valid after rising edge of MEM_CLKControl Signals, Address and MBA hold after rising edge of MEM_CLK
Min7.5—tmem_clk*0.5
—1.552Max—
tmem_clk*0.5+0.4
—4.591—
Unitsnsnsnsnsns
SpecIDA5.15A5.16A5.17A5.18A5.19
tdata_sample_maxRead Data sample windowtdata_sample_minRead Data sample window
NOTES:
1Calculated with maximum number of Tap delay, 31 Tap delay are selected.2
Calculated with minimum number of Tap delay, 0 Tap delay are selected.
MPC5200 Data Sheet, Rev. 4
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MEM_CLK
MEM_CLK
tvalid
thold
Control SignalsActiveNOPREADNOPNOPNOPNOPNOP
MDQS (Data Strobe)
tdata_valid_min
tdata_valid_max
MDQ (Data)
tdata_sample_min
tdata_sample_max
SamplepositionA
Read DataSample Window
MDQS (Data Strobe)
tdata_valid_min
tdata_valid_max
MDQ (Data)
0.5 * MEM_CLK
tdata_sample_mintdata_sample_max
SamplepositionB
Read DataSample Window
tvalid
thold
MA (Address)
tvalid
Row
thold
Column
MBA (Bank Selects)
Sample position A: data are sampled on the expected edge of MEM_CLK, the MDQS signal indicate the valid dataSample position B: data are sampled on a later edge of MEM_CLK, SDRAM controller is waiting for the vaild MDQS signalNOTE: Control Signals signals are composed of RAS, CAS, MEM_WE, MEM_CS, MEM_CS1 and CLK_EN
Figure7. Timing Diagram—DDR SDRAM Memory Read Timing
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor
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8.34delay [ns]tdata_valid_max4.59tdata_sample_mintdata_sample_mintdata_valid_minMemory Data valid windowPossible sample time over PVT for one selected Tap delay1.55Working Tap Delay rangefor sample position BWorking Tap Delay rangefor sample position A0selected Tap delay
31Tap delay number
Figure8. Read Data sample window depend on the number of Tap delay
The position of the tdata_valid window is depend on the clock / data flight time on the board. The MDQS signal indicate if the read data are valid. If the controller is not able to detect a valid MDQS signal on the sample time (sample position A) then the controller will look for valid MDQS / data on the next edge of the MEM_CLK signal (sample position B). Depend on the board travel time, different working tap delay configurations are possible. For a fast connection the data will be sampled with the next edge of MEM_CLK, this shows Figure8, sample position A. With a longer connection maybe two sample positions are possible. Figure8 shows a example with two working sample position (A and B). With a bigger board delay only sample position B will be possible.
The equation below shows how to calculate the upper and lower limit. The right Tap delay number is selected, when the possible max and min sample timing is within the memory data valid window.
•tdata_sample_max = max((1.55 + TapNum * 0.095), (1.74 + TapNum * 0.045))
•
tdata_sample_min = min((1.55 + TapNum * 0.095), (1.74 + TapNum * 0.045))
MPC5200 Data Sheet, Rev. 4
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3.3.5.4
Symtmem_clktDQSS
Memory Interface Timing-DDR SDRAM Write Command
Table21. DDR SDRAM Memory Write Timing
Description
MEM_CLK period
Delay from write command to first rising edge of MDQS
Min7.5—
Max—tmem_clk+0.4
Unitsnsns
SpecIDA5.20A5.21
MEM_CLKMEM_CLKControl SignalsWriteWriteWriteWriteMDQS (Data Strobe)tdqssMDQ (Data)NOTE: Control Signals signals are composed of RAS, CAS, MEM_WE, MEM_CS, MEM_CS1 and CLK_EN
Figure9. DDR SDRAM Memory Write Timing
3.3.6PCI
The PCI interface on the MPC5200 is designed to PCI Version 2.2 and supports 33-MHz and 66-MHz PCI operations. See the PCI Local Bus Specification [4]; the component section specifies the electrical and timing parameters for PCI components with the intent that components connect directly together whether on the planar or an expansion board, without any external buffers or other “glue logic.” Parameters apply at the package pins, not at expansion board edge connectors.
The MPC5200 is always the source of the PCI CLK. The clock waveform must be delivered to each 33-MHz or 66-MHz PCI component in the system. Figure10 shows the clock waveform and required measurement points for 3.3 V signaling environments. Table22 summarizes the clock specifications.
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor
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Tcyc
Thigh0.6VccTlow
0.4Vcc, p-to-p(minimum)
0.5Vcc0.4VccPCI CLK
0.3Vcc
0.2Vcc
Figure10. PCI CLK Waveform
Table22. PCI CLK Specifications
66 MHz
SymTcycThightlow-Description
Min
PCI CLK Cycle TimePCI CLK High TimePCI CLK Low TimePCI CLK Slew Rate
15661.5
4
1
4
V/ns
2
Max30
Min3011
Max
nsns
1,3
A6.1A6.2A6.3A6.4
33 MHz
Units
Notes
SpecID
NOTES:
1.In general, all 66-MHz PCI components must work with any clock frequency up to 66 MHz. CLK requirements vary depending upon whether the clock frequency is above 33 MHz.
2.Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate must be met across the minimum peak-to-peak portion of the clock waveform as shown in Figure10.
3.The minimum clock period must not be violated for any single clock cycle, i.e., accounting for all system jitter.
MPC5200 Data Sheet, Rev. 4
26
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Table23. PCI Timing Parameters
66 MHz
SymTval
Description
Min
CLK to Signal Valid Delay - bused signals
222
14
350
710,120
Max66
Min222
28Max1112
nsnsnsnsnsnsns
1,2,31,2,3113,43,44
A6.5A6.6A6.7A6.8A6.9A6.10A6.11
33 MHz
Units
Notes
SpecID
Tval(ptp)CLK to Signal Valid Delay - point
to pointTonToffTsu
Float to Active DelayActive to Float Delay
Input Setup Time to CLK - bused signals
Tsu(ptp)Input Setup Time to CLK - point
to pointTh
Input Hold Time from CLK
NOTES:
1.See the timing measurement conditions in the PCI Local Bus Specification [4]. It is important that all driven signal transitions drive to their Voh or Vol level within one Tcyc.
2.Minimum times are measured at the package pin with the load circuit, and maximum times are measured with the load circuit as shown in the PCI Local Bus Specification [4].
3.REQ# and GNT# are point-to-point signals and have different input setup times than do bused signals. GNT# and REQ# have a setup of 5 ns at 66 MHz. All other signals are bused.
4.See the timing measurement conditions in the PCI Local Bus Specification [4].
For Measurement and Test Conditions, see the PCI Local Bus Specification [4].
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor
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3.3.7Local Plus Bus
The Local Plus Bus is the external bus interface of the MPC5200. Maximum eight configurable
Chip-selects are provided. There are two main modes of operation: non-MUXed (Legacy and Burst) and MUXED. The reference clock is the PCI CLK. The maximum bus frequency is 66 MHz.Definition of Acronyms and Terms:WS = Wait StateDC = Dead CycleLB = Long Burst
DS = Data size in BytetPCIck = PCI clock periodtIPBIck = IPBI clock period
tPCIck
PCI CLK
tIPBIck
IPBI CLK
Figure11. Timing Diagram—IPBI and PCI clock (example ratio: 4:1)
3.3.7.1
SymtCSAtCSNt1t2t3t4t5t6t7t8t9t10t11t12t13
Non-MUXed Mode
Table24. Non-MUXed Mode Timing
Description
PCI CLK to CS assertionPCI CLK to CS negationCS pulse width
ADDR valid before CS assertionADDR hold after CS negationOE assertion before CS assertionOE negation before CS negationRW valid before CS assertionRW hold after CS negation
DATA output valid before CS assertionDATA output hold after CS negationDATA input setup before CS negationDATA input hold after CS negationACK assertion after CS assertionACK negation after CS negation
Min--(2+WS)*tPCIck
tIPBIcktIPBIck--tPCIcktIPBIcktIPBIcktIPBIck2.80tPCIck-Max1.81.8(2+WS)*tPCIck
tPCIck-0.40.4-----(DC+1)*tPCIck
-tPCIck
Unitsnsnsnsnsnsnsnsnsnsnsnsnsnsnsns
3321
NotesSpecID
A7.1A7.2A7.3A7.4A7.5A7.6A7.7A7.8A7.9A7.10A7.11A7.12A7.13A7.14A7.15
MPC5200 Data Sheet, Rev. 4
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Table24. Non-MUXed Mode Timing (continued)
Symt14t15t16t17
Description
TS assertion before CS assertionTS pulse width
TSIZ valid before CS assertionTSIZ hold after CS negation
Min-tPCIcktIPBIcktIPBIck
Max0.8tPCIck--Unitsnsnsnsns
NotesSpecID4455
A7.16A7.17A7.18A7.19
NOTES:
1.ACK can shorten the CS pulse width.
Wait States (WS) can be programmed in the Chip Select X Register, Bit field WaitP and WaitX. It can be specified from 0 - 65535.
2.In Large Flash and MOST Graphics mode the shared PCI/ATA pins, used as address lines, are released at the same moment as the CS. This can cause that the address is changing earlier as CS is deasserted. 3.ACK is input and can be used to shorten the CS pulse width.4.Only available in Large Flash and MOST Graphics mode.5.Only available in MOST Graphics mode.
t1CS[x]ADDRt2t3t4t5OER/Wt6t7t8t9DATA (wr)t10t11DATA (rd)ACKt14t15t17t12t13TSTSIZ[1:2]t16Figure12. Timing Diagram—Non-MUXed Mode
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor
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3.3.7.2
SymtCSAtCSNt1t2t3t4t5t6t7t8t9t10t11t12t13t14t15
Burst Mode
Table25. Burst Mode Timing
Description
PCI CLK to CS assertionPCI CLK to CS negationCS pulse width
ADDR valid before CS assertionADDR hold after CS negationOE assertion before CS assertionOE negation before CS negationRW valid before CS assertionRW hold after CS negationDATA setup before rising edge of PCI
DATA hold after rising edge of PCIDATA hold after CS negationACK assertion after CS assertionACK negation before CS negationACK pulse width
CS assertion after TS assertionTS pulse width
Min--Max1.81.8
UnitsNotesSpecIDnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsns
32,31,2
A7.20A7.21A7.22A7.23A7.24A7.25A7.26A7.27A7.28A7.29A7.30A7.31A7.32A7.33A7.34A7.35A7.36
(1+WS+4LB*2*(32/DS))*(1+WS+4LB*2*(32/DS))
tPCIck*tPCIck
tIPBIck---tPCIcktPCIck1.800--4LB*2*(32/DS)*tPCIck
-tPCIck
tPCIck-0.70.40.4----(DC+1)*tPCIck(WS+1)*tPCIck
0.6
4LB*2*(32/DS)*tPCIck
0.8tPCIck
NOTES:
1.Wait States (WS) can be programmed in the Chip Select X Register, Bit field WaitP and WaitX. It can be specified 0 - 65535.2.Example:
Long Burst is used, this means the CS related BERx and SLB bits of the Chip Select Burst Control Register are set and a burst on the internal XLB is executed. => LB = 1Data bus width is 8 bit. => DS = 8
=> 41*2*(32/8) = 32 => ACK is asserted for 32 PCI cycles to transfer one cache line.Wait State is set to 10. => WS = 10
1+10+32 = 43 => CS is asserted for 43 PCI cycles.3.ACK is output and indicates the burst.
MPC5200 Data Sheet, Rev. 4
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PCI CLKCS[x]ADDR
t4
t2t1
t3
t5
OE
t6t7
t8
t10R/WDATA (rd)
t9
t11
t12
t13
ACK
t14
t15
TS
Figure13. Timing Diagram—Burst Mode
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor
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3.3.7.3MUXed Mode
Table26. MUXed Mode Timing
SymtCSAtCSNtALEAt1t2t3t4t5t6t7tTSAt8t9tOEAtOENt10t11t12t13
Description
PCI CLK to CS assertionPCI CLK to CS negationPCI CLK to ALE assertion
ALE assertion before Address, Bank, TSIZ assertion
CS assertion before Address, Bank, TSIZ negation
CS assertion before Data wr validData wr hold after CS negationData rd setup before CS negationData rd hold after CS negationALE pulse width
CS assertion after TS assertionTS pulse widthCS pulse width
OE assertion before CS assertionOE negation before CS negationRW assertion before ALE assertionRW negation after CS negationACK assertion after CS assertionACK negation after CS negation
Min------tIPBIck2.80---(2+WS)*tPCIck
--tIPBIck-tIPBIck-Max1.81.810.80.70.7--(DC+1)*tPCIck
tPCIck0.8tPCIck(2+WS)*tPCIck
0.40.4-tPCIck-tPCIck
Unitsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsns
221Notes
SpecIDA7.15A7.16A7.16A7.17A7.18A7.19A7.20A7.21A7.22A7.23A7.24A7.24A7.25A7.26A7.27A7.26A7.27A7.28A7.28
Note:
1.ACK can shorten the CS pulse width.
Wait States (WS) can be programmed in the Chip Select X Register, Bit field WaitP and WaitX. It can be specified 0 - 65535.2.ACK is input and can be used to shorten the CS pulse width.
MPC5200 Data Sheet, Rev. 4
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PCI CLKt1t2t4AD[31,27] (wr)AD[30:28] (wr)AD[26:25] (wr)AD[24:0] (wr)AD[31:0] (rd)t7DataTSIZ[0:2] bitsDataDataDatat3t5t6Bank[0:1] bitsAddress[7:31]DataALEAddress latcht8TSt9CSxOEt10t11RWACKAddress tenuret12t13Data tenureFigure14. Timing Diagram—MUXed Mode
3.3.8ATA
The MPC5200 ATA Controller is completely software programmable. It can be programmed to operate with ATA protocols using their respective timing, as described in the ANSI ATA-4 specification. The ATA interface is completely asynchronous in nature. Signal relationships are based on specific fixed timing in terms of timing units (nano seconds).
ATA data setup and hold times, with respect to Read/Write strobes, are software programmable inside the ATA Controller. Data setup and hold times are implemented using counters. The counters count the number of ATA clock cycles needed to meet the ANSI ATA-4 timing specifications. For details, see the ANSI ATA-4 specification [5] and how to program an ATA Controller and ATA drive for different ATA protocols and their respective timing. See the MPC5200 User Manual [1].
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor
33
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Electrical and Thermal Characteristics
The MPC5200 ATA Host Controller design makes data available coincidentally with the active edge of the WRITE strobe in PIO and Multiword DMA modes.
• Write data is latched by the drive at the inactive edge of the WRITE strobe. This gives ample
setup-time beyond that required by the ATA-4 specification.
•Data is held unchanged until the next active edge of the WRITE strobe. This gives ample
hold-time beyond that required by the ATA-4 specification.All ATA transfers are programmed in terms of system clock cycles (IP bus clocks) in the ATA Host Controller timing registers. This puts constraints on the ATA protocols and their respective timing modes in which the ATA Controller can communicate with the drive.
Faster ATA modes (i.e., UDMA 0, 1, 2) are supported when the system is running at a sufficient frequency to provide adequate data transfer rates. Adequate data transfer rates are a function of the following:
•The MPC5200 operating frequency (IP bus clock frequency)•Internal MPC5200 bus latencies
•Other system load dependent variablesThe ATA clock is the same frequency as the IP bus clock in MPC5200. See the MPC5200 User Manual [1].
NOTE
All output timing numbers are specified for nominal 50 pF loads.
Table27. PIO Mode Timing Specifications
PIO Timing Parameter
t0t1t2t2it3t4t5t6t9tAtB
Cycle Time
Address valid to DIOR/DIOW setupDIOR/DIOW pulse width 16-bit8-bit
DIOR/DIOW recovery timeDIOW data setupDIOW data holdDIOR data setupDIORdataholdDIOR/DIOW to addressvalid holdIORDY setupIORDY pulse width
Min/Max(ns)minminminminminminminminminminmaxmax
Mode 0(ns)60070165290—603050520351250
Mode 1(ns)38350125290—452035515351250
Mode 2(ns)24030100290—301520510351250
Mode 3(ns)18030808070301020510351250
Mode 4(ns)12025707025201020510351250
SpecIDA8.1A8.2A8.3A8.4A8.5A8.6A8.7A8.8A8.9A8.10A8.11
MPC5200 Data Sheet, Rev. 4
34
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Electrical and Thermal Characteristics
CS[0]/CS[3]/DA[2:0]
t2DIOR/DIOW
t1t0t9t8t3
WDATA
t5
RDATA
t4
t6
tA
IORDY
tB
Figure15. PIO Mode Timing
Table28. Multiword DMA Timing Specifications
Multiword DMA Timing Parameters
t0tCtDtEtGtFtHtItJtKrtKwtLrtLw
Cycle Time
DMACK to DMARQ delayDIOR/DIOW pulse width (16-bit)DIOR data accessDIOR/DIOW data setupDIOR data holdDIOW data holdDMACK to DIOR/DIOW setupDIOR/DIOW to DMACK holdDIOR negated pulse widthDIOW negated pulse widthDIOR to DMARQ delayDIOW to DMARQ delayMin/Maxminmaxminmaxminminminminminminminmaxmax
Mode 0(ns)
480—2151501005200205021512040
Mode 1(ns)
150—8060305150550504040
Mode 2(ns)
120—7050205100525253535
SpecIDA8.12A8.13A8.14A8.15A8.16A8.17A8.18A8.19A8.20A8.21A8.22A8.23A8.24
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor
35
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Electrical and Thermal Characteristics
t0DMARQ
(Drive)
tC
DMACK(Host)
tI
DIORDIOW(Host)
tE
RDATA(Drive)
tS
tF
WDATA(Host)
tD
tK
tL
tJ
tGtH
NOTE:Thedirectionofsignalassertionistowardsthetop of the page, and the direction of negation istowards the bottom of the page, irrespective of theelectrical properties of the signal.
Figure16. Multiword DMA TimingTable29. Ultra DMA Timing Specification
MODE 0(ns)Min
(t)2CYC(t)CYC(t)2CYC
240114235
Max———
MODE 1(ns)Min16075156
Max———
MODE 2(ns)Min12055117
Max———
Typical sustained average two cycle time.
A8.26A8.27A8.28
NameCommentSpecID
For information only, do not test.
Cycle time allowing for asymmetry and clock variations from STROBE edge to STROBE edgeTwo-cycle time allowing for clock variations, from rising edge to next rising edge or from falling edge to next falling edge of STROBE.Data setup time at recipient.Dataholdtimeatrecipient.
Data valid setup time at sender, to STROBE edge.Data valid hold time at sender, from STROBE edge.First STROBE time for drive to first negate DSTROBE from STOP during a data-in burst.
(t)DS(t)DH(t)DVS(t)DVH(t)FS
1557060
————230
10860
————200
753460
————170
A8.29A8.30A8.31A8.32A8.33
MPC5200 Data Sheet, Rev. 4
36
Freescale Semiconductor
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Electrical and Thermal Characteristics
Table29. Ultra DMA Timing Specification (continued)
MODE 0(ns)Min
(t)LI(t)MLI(t)UI(t)AZ(t)ZAH(t)ZAD(t)ENV(t)SR
0200—20020—
Max150——10——7050
MODE 1(ns)Min0200—20020—
Max150——10——7030
MODE 2(ns)Min0200—20020—
Max150——10——7020
LimitedInterlocktime.1,2Interlock time with minimum.1,2Unlimited interlock time. 1,2Maximum time allowed for output drivers to release from being asserted or negated
Minimum delay time required for output drivers to assert or negate from released stateEnvelope time—from DMACK to STOP and HDMARDY during data out burst initiation.STROBE to DMARDY time, if DMARDY is negated before this long after STROBE edge, the recipient receives no more than one additional data word.Ready-to-Final STROBE time—no STROBE edges are sent this long after negation of DMARDY.Ready-to-Pause time—the time recipient waits to initiate pause after negating DMARDY.
Pull-up time before allowing IORDY to be released.Minimum time drive waits before driving IORDYSetup and hold times for DMACK, before assertion or negation.
Time from STROBE edge to negation of DMARQ or assertion of STOP, when sender terminates a burst.
A8.34A8.35A8.36A8.37A8.38A8.39A8.40A8.41
NameCommentSpecID
(t)RFS(t)RP(t)IORDYZ(t)ZIORDY(t)ACK(t)SS
—160—02050
75—20———
—125—02050
60—20———
—100—02050
50—20———
A8.42A8.43A8.44A8.45A8.46A8.47
NOTES:1t, t
UIMLI, tLI indicate sender-to-recipient or recipient-to-sender interlocks. That is, one agent (either sender or recipient) is waiting for the other agent to respond with a signal before proceeding. •tUI is an unlimited interlock that has no maximum time value.•tMLI is a limited time-out that has a defined minimum.•tLI is a limited time-out that has a defined maximum.2
All timing parameters are measured at the connector of the drive to which the parameter applies. For example, the sender shall stop generating STROBE edges tRFS after negation of DMARDY. Both STROBE and DMARDY timing measurements are taken at the connector of the sender. Even though the sender stops generating STROBE edges, the receiver may receive additional STROBE edges due to propagation delays. All timing measurement switching points (low to high and high to low) are taken at 1.5 V.
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor
37
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Electrical and Thermal Characteristics
DMARQ(device)
tUI
DMACK(device)
tACK
STOP(host)
tACK
HDMARDY(host)
tZIORDY
DSTROBE(device)
tAZ
DD(0:15)
tACK
DA0, DA1, DA2,CS[0:1]1
tDVS
tDVH
tENVtENV
tZAD
tFStFS
tZAD
Figure17. Timing Diagram—Initiating an Ultra DMA Data In Burst
t2CYC
tCYC
DSTROBEat device
tDVH
DD(0:15)at deviceDSTROBEat host
tDH
DD(0:15)at host
tDS
tDH
tDS
tDH
tDVS
tDVH
tDVS
tDVH
tCYC
t2CYC
Figure18. Timing Diagram—Sustained Ultra DMA Data In Burst
MPC5200 Data Sheet, Rev. 4
38
Freescale Semiconductor
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Electrical and Thermal Characteristics
DMARQ(device)DMARQ(host)STOP(host)HDMARDY(host)
tSR
tRFS
DSTROBE(device)DD[0:15](device)
tRP
Figure19. Timing Diagram—Host Pausing an Ultra DMA Data In Burst
DMARQ(device)DMACK(host)STOP(host)
tLI
HDMARDY(host)DSTROBE(device)
tACK
tLItLItMLItACK
tSS
tIORDYZ
tZAH
tAZ
tDVS
tDVH
CRC
tACK
DD[0:15]DA0,DA1,DA2,
CS[0:1]
Figure20. Timing Diagram—Drive Terminating Ultra DMA Data In Burst
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor
39
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Electrical and Thermal Characteristics
DMARQ(device)
tLI
DMACK(host)
tMLI
tRPtZAHtACK
STOP(host)
tAZtACK
HDMARDY(host)
tRFS
DSTROBE(device)
tLI
tMLI
tIORDYZ
tDVS
tDVH
DD[0:15]DA0,DA1,DA2,
CS[0:1]
CRC
tACK
Figure21. Timing Diagram—Host Terminating Ultra DMA Data In Burst
MPC5200 Data Sheet, Rev. 4
40
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Electrical and Thermal Characteristics
DMARQ(device)DMACK(host)
tUI
tACK
STOP(host)
tZIORDY
DDMARDY(host)
tACK
HSTROBE(device)
tENV
tLItUI
tDVS
tDVH
DD[0:15](host)
tACK
DA0,DA1,DA2,
CS[0:1]
Figure22. Timing Diagram—Initiating an Ultra DMA Data Out Burst
t2CYC
tCYC
HSTROBE(host)
tDVH
DD[0:15](host)HSTROBE(device)
tDH
DD[0:15](device)
tDS
tDH
tDS
tDH
tDVS
tDVH
tDVS
tDVH
tCYC
t2CYC
Figure23. Timing Diagram—Sustained Ultra DMA Data Out Burst
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor
41
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Electrical and Thermal Characteristics
tRP
DMARQ(device)DMACK(host)STOP(host)
tSR
DDMARDY(device)
tRFS
HSTROBEDD[0:15]
(host)
Figure24. Timing Diagram—Drive Pausing an Ultra DMA Data Out Burst
DMARQ(device)
tLI
DMACK(host)
tSS
STOP(host)
tLI
DDMARDY(device)
tACK
HSTROBE(host)
tDVS
DD[0:15](host)DA0,DA1,DA2,
CS[0:1]
CRC
tACK
tDVHtIORDYZ
tLI
tACK
tMLI
Figure25. Timing Diagram—Host Terminating Ultra DMA Data Out Burst
MPC5200 Data Sheet, Rev. 4
42
Freescale Semiconductor
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Electrical and Thermal Characteristics
DMARQ(device)DMACK(host)
tLI
STOP(host)
tRP
DDMARDY(device)
tRFS
HSTROBE(host)
tDVS
DD[0:15](host)
CRC
tACK
tDVH
tLI
tMLI
tACK
tIORDYZ
tMLI
tACK
DA0,DA1,DA2,
CS[0:1]
Figure26. Timing Diagram—Drive Terminating Ultra DMA Data Out Burst
Table30. Timing Specification ata_isolation
Sym12
Description
ata_isolation setup timeata_isolation hold time
Min7-Max-19
UnitsIP Bus cyclesIP Bus cycles
SpecIDA8.48A8.49
DIOR
ATA_ISOLATION
12Figure27. Timing Diagram-ATA-ISOLATION
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor
43
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Electrical and Thermal Characteristics
3.3.9Ethernet
AC Test Timing Conditions:•Output LoadingAll Outputs: 25 pF
Table31. MII Rx Signal Timing
SymM1M2M3M4
Description
RXD[3:0], RX_DV, RX_ER to RX_CLK setupRX_CLK to RXD[3:0], RX_DV, RX_ER holdRX_CLK pulse width highRX_CLK pulse width low
Min101035%35%
Max——65%65%
Unitnsns
RX_CLK Period1RX_CLK Period1
SpecIDA9.1A9.2A9.3A9.4
NOTES:
1RX_CLK shall have a frequency of 25% of data rate of the received signal. See the IEEE 802.3 Specification [6].
M3
RX_CLK (Input)
M4
RXD[3:0] (inputs)
RX_DVRX_ER
M1M2
Figure28. Ethernet Timing Diagram—MII Rx Signal
MPC5200 Data Sheet, Rev. 4
44
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Electrical and Thermal Characteristics
Table32. MII Tx Signal Timing
SymM5M6M7
Description
TX_CLK rising edge to TXD[3:0], TX_EN, TX_ER Delay
TX_CLK pulse width highTX_CLK pulse width low
Min035%35%
Max2565%65%
Unitns
TX_CLK Period1TX_CLK Period(1)SpecIDA9.5A9.6A9.7
NOTES:
1the TX_CLK frequency shall be 25% of the nominal transmit frequency, e.g., a PHY operating at 100 Mb/s must provide a TX_CLK frequency of 25 MHz and a PHY operating at 10 Mb/s must provide a TX_CLK frequency of 2.5 MHz. See the IEEE 802.3 Specification [6].
M6
TX_CLK (Input)
M5
TXD[3:0] (Outputs)
TX_ENTX_ER
M7
Figure29. Ethernet Timing Diagram—MII Tx Signal
Table33. MII Async Signal Timing
Sym
Description
Min
Max
Unit
SpecID
M8CRS, COL minimum pulse width1.5—TX_CLK PeriodA9.8
CRS, COL
M8
Figure30. Ethernet Timing Diagram—MII Async
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor
45
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Electrical and Thermal Characteristics
Table34. MII Serial Management Channel Signal Timing
SymM9M10M11M12M13M14
Description
MDC falling edge to MDIO output delayMDIO (input) to MDC rising edge setupMDIO (input) to MDC rising edge holdMDC pulse width high1MDC pulse width low(1)MDC period2Min01010160160400
Max25—————
Unitnsnsnsnsnsns
SpecIDA9.9A9.10A9.11A9.12A9.13A9.14
NOTES:1
MDC is generated by MPC5200 with a duty cycle of 50% except when MII_SPEED in the FEC MII_SPEED control register is changed during operation. See the MPC5200 User Manual [1].
2The MDC period must be set to a value of less then or equal to 2.5 MHz (to be compliant with the IEEE MII characteristic) by programming the FEC MII_SPEED control register. See the MPC5200 User Manual [1].
M12
M13
MDC (Output)
M14
M9
MDIO (Output)
MDIO (Input)
M10M11
Figure31. Ethernet Timing Diagram—MII Serial Management
3.3.10USB
Table35. Timing Specifications—USB Output Line
Sym1234
USB Bit width1Transceiver enable timeSignal falling timeSignal rising time
Description
Min83.383.3——
Max6676677.97.9
Unitsnsnsnsns
SpecIDA10.1A10.2A10.3A10.4
NOTES:
1Defined in the USB config register, (12 Mbit/s or 1.5 Mbit/s mode).
MPC5200 Data Sheet, Rev. 4
46
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Electrical and Thermal Characteristics
NOTE
Output timing was specified at a nominal 50 pF load.
2
USB_OE
3
USB_TXN
1
USB_TXP
1
4
4
3
Figure32. Timing Diagram—USB Output Line
3.3.11SPI
Table36. Timing Specifications — SPI Master Mode, Format 0 (CPHA = 0)
Sym12345671011
Cycle time
Clock high or low timeSlave select clock delay
Output Data valid after Slave Select (SS)Output Data valid after SCKInput Data setup timeInput Data hold timeSlave disable lag time Sequential transfer delayClock falling timeClock rising time
DescriptionMin4215.0——20.020.015.01——
Max1024512—20.020.0————7.97.9
UnitsIP-Bus Cycle1IP-Bus Cycle1
nsnsnsnsnsnsIP-Bus Cycle1
nsns
SpecIDA11.1A11.2A11.3A11.4A11.5A11.6A11.7A11.8A11.9A11.10A11.11
NOTES:1
Inter Peripheral Clock is defined in the MPC5200 User Manual [1].
NOTE
Output timing was specified at a nominal 50 pF load.
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor
47
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Electrical and Thermal Characteristics
1
10
SCK
(CLKPOL=0)
OutputSCK
(CLKPOL=1)
Output
3
SSOutput
4
MOSIOutput
6
MISOInput
7
7
65
11
22
11
10
Figure33. Timing Diagram — SPI Master Mode, Format 0 (CPHA = 0)Table37. Timing Specifications — SPI Slave Mode, Format 0 (CPHA = 0)
Sym1234567
Cycle time
Clock high or low timeSlave select clock delay
Output Data valid after Slave Select (SS)Output Data valid after SCKInput Data setup timeInput Data hold timeSlave disable lag time Sequential Transfer delay
Description
Min4215.0——50.00.015.01
Max1024512—50.050.0————
UnitsIP-Bus Cycle1IP-Bus Cycle1
nsnsnsnsnsnsIP-Bus Cycle1
SpecIDA11.12A11.13A11.14A11.15A11.16A11.17A11.18A11.19A11.20
NOTES:1
Inter Peripheral Clock is defined in the MPC5200 User Manual [1].
NOTE
Output timing was specified at a nominal 50 pF load.
MPC5200 Data Sheet, Rev. 4
48
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Electrical and Thermal Characteristics
1
SCK
(CLKPOL=0)
InputSCK
(CLKPOL=1)
Input
3
SSInput
6
MOSIInput
4
MISOOutput
Figure34. Timing Diagram — SPI Slave Mode, Format 0 (CPHA = 0)Table38. Timing Specifications — SPI Master Mode, Format 1 (CPHA = 1)
Sym123456710
Cycle time
Clock high or low timeSlave select clock delayOutput data validInput Data setup timeInput Data hold timeSlave disable lag time Sequential Transfer delayClock falling timeClock rising time
Description
Min4215.0—20.020.015.01——
Max1024512—20.0————7.97.9
UnitsIP-Bus Cycle1IP-Bus Cycle1
nsnsnsnsnsIP-Bus Cycle1
nsns
SpecIDA11.21A11.22A11.23A11.24A11.25A11.26A11.27A11.28A11.29A11.30
22
7
5
NOTES:
1Inter Peripheral Clock is defined in the MPC5200 User Manual [1].
NOTE
Output timing was specified at a nominal 50 pF load.
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor
49
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Electrical and Thermal Characteristics
1
9
SCK
(CLKPOL=0)
OutputSCK
(CLKPOL=1)
Output
3
SSOutput
1022
10
9
78
4
MOSIOutput
5
MISOInput
6
Figure35. Timing Diagram — SPI Master Mode, Format 1 (CPHA = 1)Table39. Timing Specifications — SPI Slave Mode, Format 1 (CPHA = 1)
Sym12345678
Cycle time
Clock high or low timeSlave select clock delayOutput data validInput Data setup timeInput Data hold timeSlave disable lag time Sequential Transfer delay
Description
Min4215.0—50.00.015.01
Max1024512—50.0————
Units
SpecID
IP-Bus Cycle1A11.31IP-Bus Cycle1A11.32
nsnsnsnsns
A11.33A11.34A11.35A11.36A11.37
IP-Bus Cycle1A11.38
NOTES:1
Inter Peripheral Clock is defined in the MPC5200 User Manual [1].
NOTE
Output timing was specified at a nominal 50 pF load.
MPC5200 Data Sheet, Rev. 4
50
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Electrical and Thermal Characteristics
1
SCK
(CLKPOL=0)
InputSCK
(CLKPOL=1)
Input
3
SSInput
5
MOSIInput
4
MISOOutput
Figure36. Timing Diagram — SPI Slave Mode, Format 1 (CPHA = 1)
22
78
6
3.3.12MSCAN
The CAN functions are available as RX and TX pins at normal IO pads (I2C1+GPTimer or PSC2). There is no filter for the WakeUp dominant pulse. Any High-to-Low edge can cause WakeUp, if configured.
3.3.13I2C
Table40. I2C Input Timing Specifications—SCL and SDA
Sym12467
Description
Start condition hold timeClock low periodData hold timeClock high timeData setup time
Start condition setup time (for repeated start condition only)
Stop condition setup time
Min280.040.022
Max———————
UnitsIP-Bus Cycle1IP-Bus Cycle1
nsIP-Bus Cycle1
nsIP-Bus Cycle1IP-Bus Cycle1
SpecIDA13.1A13.2A13.3A13.4A13.5A13.6A13.7
NOTES:
1Inter Peripheral Clock is defined in the MPC5200 User Manual [1].
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor
51
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Electrical and Thermal Characteristics
Table41. I2C Output Timing Specifications—SCL and SDA
Sym112132415161718191
Description
Start condition hold timeClock low periodSCL/SDA rise timeData hold timeSCL/SDA fall timeClock high timeData setup time
Start condition setup time (for repeated start condition only)
Stop condition setup time
Min610—7—1022010
Max——7.9—7.9————
UnitsIP-Bus Cycle3IP-Bus Cycle3
nsIP-Bus Cycle3
nsIP-Bus Cycle3IP-Bus Cycle3IP-Bus Cycle3IP-Bus Cycle3SpecIDA13.8A13.9A13.10A13.11A13.12A13.13A13.14A13.15A13.16
NOTES:
1Programming IFDR with the maximum frequency (IFDR=0x20) results in the minimum output timings listed. The I2C interface is designed to scale the data transition time, moving it to the middle of the SCL low period. The actual position is affected by the prescale and division values programmed in IFDR.2
Because SCL and SDA are open-drain-type outputs, which the processor can only actively drive low, the time SCL or SDA takes to reach a high level depends on external signal capacitance and pull-up resistor values3Inter Peripheral Clock is defined in the MPC5200 User Manual [1].
NOTE
Output timing was specified at a nominal 50 pF load.
2
SCL
1
SDA
Figure37. Timing Diagram—I2C Input/Output
4
7
8
3
9
6
5
3.3.14J1850
See the MPC5200 User Manual [1].
MPC5200 Data Sheet, Rev. 4
52
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Electrical and Thermal Characteristics
3.3.15PSC
3.3.15.1Codec Mode (8,16,24 and 32-bit) / I2S Mode
Table42. Timing Specifications—8,16, 24 and 32-bit CODEC / I2S Master Mode
Sym12345678
Description
Bit Clock cycle time, programmed in CCS registerClock pulse widthBit Clock fall timeBit Clock rise time
FrameSync valid after clock edgeFrameSync invalid after clock edgeOutput Data valid after clock edgeInput Data setup time
Min40.0——————6.0
Typ—50——————
Max——7.97.98.48.49.3—
Unitsns%1nsnsnsnsnsns
SpecIDA15.1A15.2A15.3A15.4A15.5A15.6A15.7A15.8
NOTES:
1Bit Clock cycle time
NOTE
Output timing was specified at a nominal 50 pF load.
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor
53
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Electrical and Thermal Characteristics
1
BitClk
(CLKPOL=0)
OutputBitClk
(CLKPOL=1)
Output
5
Frame
(SyncPol = 1)
OutputFrame
(SyncPol = 0)
Output
7
TxDOutput
8
RxDInput
Figure38. Timing Diagram — 8,16, 24, and 32-bit CODEC / I2S Master ModeTable43. Timing Specifications — 8,16, 24, and 32-bit CODEC / I2S Slave Mode
Sym123456
Bit Clock cycle timeClock pulse widthFrameSync setup time
Output Data valid after clock edgeInput Data setup timeInput Data hold time
Description
Min40.0—1.0—1.01.0
Typ—50————
Max———14.0——
Unitsns%1nsnsnsns
SpecIDA15.9A15.10A15.11A15.12A15.13A15.14
22
3
4
4
3
6NOTES:1
Bit Clock cycle time
NOTE
Output timing was specified at a nominal 50 pF load.
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor
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Electrical and Thermal Characteristics
1
BitClk
(CLKPOL=0)
InputBitClk
(CLKPOL=1)
Input
3
Frame
(SyncPol = 1)
InputFrame
(SyncPol = 0)
Input
4
TxDOutput
5
RxDInput
6
Figure39. Timing Diagram — 8,16, 24, and 32-bit CODEC / I2S Slave Mode
22
3.3.15.2AC97 Mode
Table44. Timing Specifications — AC97 Mode
Sym1234567
Bit Clock cycle timeClock pulse high timeClock pulse low time
Frame valid after rising clock edgeOutput Data valid after rising clock edgeInput Data setup timeInput Data hold time
Description
Min—————1.01.0
Typ81.440.740.7————
Max———13.014.0——
Unitsnsnsnsnsnsnsns
SpecIDA15.15A15.16A15.17A15.18A15.19A15.20A15.21
NOTE
Output timing was specified at a nominal 50 pF load.
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor
55
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Electrical and Thermal Characteristics
1
BitClk
(CLKPOL=0)
InputSync
(SyncPol = 1)
Output
Sdata_out
Output
6Sdata_in
Input
7
4
32
5
Figure40. Timing Diagram — AC97 Mode
3.3.15.3IrDA Mode
Table45. Timing Specifications — IrDA Transmit Line
Sym1234
Description
Pulse high time, defined in the IrDA protocol definitionPulse low time, defined in the IrDA protocol definitionTransmitter rising timeTransmitter falling time
Min0.1250.125——
Max10000100007.97.9
Unitsµsµsnsns
SpecIDA15.22A15.23A15.24A15.25
NOTE
Output timing was specified at a nominal 50 pF load.
4
IrDA_TX
(SIR / FIR / MIR)
12
3
Figure41. Timing Diagram — IrDA Transmit Line
MPC5200 Data Sheet, Rev. 4
56
Freescale Semiconductor
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Electrical and Thermal Characteristics
3.3.15.4SPI Mode
Table46. Timing Specifications — SPI Master Mode, Format 0 (CPHA = 0)
Sym12345671011
Description
SCK cycle time, programable in the PSC CCS registerSCK pulse width, 50% SCK cycle time
Slave select clock delay, programable in the PSC CCS registerOutput Data valid after Slave Select (SS)Output Data valid after SCKInput Data setup timeInput Data hold timeSlave disable lag time
Sequential Transfer delay, programable in the PSC CTUR / CTLR register
Clock falling timeClock rising time
Min30.015.030.0——6.01.0—15.0——
Max———8.98.9——8.9—7.97.9
Unitsnsnsnsnsnsnsnsnsnsnsns
SpecIDA15.26A15.27A15.28A15.29A15.30A15.31A15.32A15.33A15.34A15.35A15.36
NOTE
Output timing was specified at a nominal 50 pF load.
1
10
SCK
(CLKPOL=0)
OutputSCK
(CLKPOL=1)
Output
3
SSOutput
4
MOSIOutput
6
MISOInput
7
7
65
11
22
11
10
Figure42. Timing Diagram — SPI Master Mode, Format 0 (CPHA = 0)
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor
57
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Electrical and Thermal Characteristics
Table47. Timing Specifications — SPI Slave Mode, Format 0 (CPHA = 0)
Sym1234567
Description
SCK cycle time, programable in the PSC CCS registerSCK pulse width, 50% SCK cycle timeSlave select clock delayInput Data setup timeInput Data hold timeOutput data valid after SSOutput data valid after SCKSlave disable lag time
Minimum Sequential Transfer delay = 2 * IP Bus clock cycle time
Min30.015.01.01.01.0——0.030.0
Max—————14.014.0——
Unitsnsnsnsnsnsnsnsns—
SpecIDA15.37A15.38A15.39A15.40A15.41A15.42A15.43A15.44A15.45
NOTE
Output timing was specified at a nominal 50 pF load.
1
SCK
(CLKPOL=0)
InputSCK
(CLKPOL=1)
Input
3
SSInput
4
MOSIInput
6
MISOOutput
7
5
22
Figure43. Timing Diagram — SPI Slave Mode, Format 0 (CPHA = 0)
MPC5200 Data Sheet, Rev. 4
58
Freescale Semiconductor
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Electrical and Thermal Characteristics
Table48. Timing Specifications — SPI Master Mode, Format 1 (CPHA = 1)
Sym123456710
Description
SCK cycle time, programable in the PSC CCS registerSCK pulse width, 50% SCK cycle time
Slave select clock delay, programable in the PSC CCS registerOutput data validInput Data setup timeInput Data hold timeSlave disable lag time
Sequential Transfer delay, programable in the PSC CTUR / CTLR register
Clock falling timeClock rising time
Min30.015.030.0—6.01.0—15.0——
Max———8.9——8.9—7.97.9
Unitsnsnsnsnsnsnsnsnsnsns
SpecIDA15.46A15.47A15.48A15.49A15.50A15.51A15.52A15.53A15.A15.55
NOTE
Output timing was specified at a nominal 50 pF load.
1
9
SCK
(CLKPOL=0)
OutputSCK
(CLKPOL=1)
Output
3
SSOutput
10
22
10
9
78
4
MOSIOutput
5
MISOInput
6
Figure44. Timing Diagram — SPI Master Mode, Format 1 (CPHA = 1)
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor
59
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Electrical and Thermal Characteristics
Table49. Timing Specifications — SPI Slave Mode, Format 1 (CPHA = 1)
Sym12345678
Description
SCK cycle time, programable in the PSC CCS registerSCK pulse width, 50% SCK cycle timeSlave select clock delayOutput data validInput Data setup timeInput Data hold timeSlave disable lag time
Minimum Sequential Transfer delay = 2 * IP-Bus clock cycle time
Min30.015.00.0—2.01.00.030.0
Max———14.0————
Unitsnsnsnsnsnsnsnsns
SpecIDA15.56A15.57A15.58A15.59A15.60A15.61A15.62A15.63
NOTE
Output timing was specified at a nominal 50 pF load.
1
SCK
(CLKPOL=0)
InputSCK
(CLKPOL=1)
Input
3
SSInput
5
MOSIInput
4
MISOOutput
Figure45. Timing Diagram — SPI Slave Mode, Format 1 (CPHA = 1)
22
78
6
MPC5200 Data Sheet, Rev. 4
60
Freescale Semiconductor
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Electrical and Thermal Characteristics
3.3.16GPIOs and Timers
3.3.16.1General and Asynchronous Signals
The MPC5200 contains several sets if I/Os that do not require special setup, hold, or valid requirements. Most of these are asynchronous to the system clock. The following numbers are provided for test and validation purposes only, and they assume a 133 MHz internal bus frequency.Figure46 shows the GPIO Timing Diagram. Table50 gives the timing specifications.
Table50. Asynchronous Signals
SymtCKtIStIHtDVtDH
Clock Period
Input Setup for Async SignalInput Hold for Async SignalsOutput ValidOutput Hold
Description
Min7.52121—1
Max———15.33—
Unitsnsnsnsnsns
SpecIDA16.1A16.2A16.3A16.4A16.5
tCKtDVOutputtISvalidvalid
tIHtDHInput
Figure46. Timing Diagram—Asynchronous Signals
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor
61
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Electrical and Thermal Characteristics
3.3.17IEEE 1149.1 (JTAG) AC Specifications
Table51. JTAG Timing Specification
Sym—123456710111213
1
Characteristic
TCK frequency of operation.TCK cycle time.
TCK clock pulse width measured at 1.5V.TCK rise and fall times.
TRST setup time to tck falling edge1.TRST assert time.Input data setup time2.Input data hold time2.TCK to output data valid3. TCK to output high impedance3.TMS, TDI data setup time.TMS, TDI data hold time.TCK to TDO data valid.TCK to TDO high impedance.
Min0401.080105515005100
Max25——3————3030——1515
UnitMHznsnsnsnsnsnsnsnsnsnsnsnsns
SpecIDA17.1A17.2A17.3A17.4A17.5A17.6A17.7A17.8A17.9A17.10A17.11A17.12A17.13A17.14
NOTES:
TRST is an asynchronous signal. The setup time is for test purposes only.2Non-test, other than TDI and TMS, signal input timing with respect to TCK.3Non-test, other than TDO, signal output timing with respect to TCK.
1
2
TCK
VM
VM
2
VM
33
VM=Midpoint Voltage
Numbers shown reference Table 51.
Figure47. Timing Diagram—JTAG Clock Input
MPC5200 Data Sheet, Rev. 4
62
Freescale Semiconductor
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Electrical and Thermal Characteristics
TCK
4
TRST
5
Numbers shown reference Table 51.
Figure48. Timing Diagram—JTAG TRST
TCK
6
DATA INPUTS
8
DATA OUTPUTS
9
DATA OUTPUTS
Numbers shown reference Table 51.
OUTPUT DATA VALID
7
INPUT DATA VALID
Figure49. Timing Diagram—JTAG Boundary Scan
TCK
10
TDI, TMS
12
TDO
13
TDO
Numbers shown reference Table 51.
OUTPUT DATA VALID
11
INPUT DATA VALID
Figure50. Timing Diagram—Test Access Port
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor
63
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Package Description
4
4.1
Package Description
Package Parameters
The MPC5200 uses a 27 mm x 27 mm TE-PBGA package. The package parameters are as provided in the following list:
•Package outline27 mm x 27 mm•Interconnects272•Pitch1.27 mm
4.2Mechanical Dimensions
Figure51 provides the mechanical dimensions, top surface, side profile, and pinout for the MPC5200, 272 TE-PBGA package.
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor
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Package DescriptionPIN A1INDEXDC4X0.2A272X0.2AEE20.35AD2BTOP VIEW(D1)19X0.2MABCNOTES:1.DIMENSIONS AND TOLERANCING PER ASMEY14.5M, 1994.2.DIMENSIONS IN MILLIMETERS.3.DIMENSION IS MEASURED AT THE MAXIMUMSOLDER BALL DIAMETER PARALLEL TOPRIMARY DATUM A.4.PRIMARY DATUM A AND THE SEATING PLANEARE DEFINED BY THE SPHERICAL CROWNS OFTHE SOLDER BALLS.MILLIMETERSMINMAX2.052.650.500.700.500.701.051.250.600.9027.00 BSC24.13 REF23.3024.7027.00 BSC24.13 REF23.3024.701.27 BSCeYWVUTRPNMLKJHGFEDCBA19XeDIMAA1A2A3bDD1D2EE1E2e(E1)4Xe/2A1A3A2ASIDE VIEW272X12345671011121314151617181920b30.3MMBOTTOM VIEWABCA0.15CASE 1135A–01ISSUE BDATE 10/15/1997Figure51. Mechanical Dimensions and Pinout Assignments for the MPC5200, 272 TE-PBGAMPC5200 Data Sheet, Rev. 4Freescale Semiconductor65元器件交易网www.cecb2b.com
Package Description
4.3Pinout Listings
Table52. MPC5200 Pinout Listing
Name
Alias
Type
Power SupplySDRAM
Output Driver
Type
Input Type
Pull-up/down
See details in the MPC5200 User Manual [1].
MEM_CASMEM_CLK_ENMEM_CSMEM_DQM[3:0]MEM_MA[12:0]MEM_MBA[1:0]MEM_MDQS[3:0]MEM_MDQ[31:0]MEM_CLKMEM_CLKMEM_RASMEM_WECASCLK_EN
I/OI/OI/O
VDD_MEM_IOVDD_MEM_IOVDD_MEM_IOVDD_MEM_IOVDD_MEM_IOVDD_MEM_IOVDD_MEM_IOVDD_MEM_IOVDD_MEM_IOVDD_MEM_IOVDD_MEM_IOVDD_MEM_IOPCI
DRV16_MEMDRV16_MEMDRV16_MEMDRV16_MEMDRV16_MEMDRV16_MEMDRV16_MEMDRV16_MEMDRV16_MEMDRV16_MEMDRV16_MEMDRV16_MEM
TTLTTLTTLTTLTTLTTLTTLTTLTTLTTLTTLTTL
DQMMAMBAMDQSMDQ
I/OI/OI/OI/OI/OI/OI/O
RASI/OI/O
EXT_AD[31:0]PCI_CBE_0PCI_CBE_1PCI_CBE_2PCI_CBE_3PCI_CLOCKPCI_DEVSELPCI_FRAMEPCI_GNTPCI_IDSELPCI_IRDYPCI_PARPCI_PERRPCI_REQPCI_RESETPCI_SERRPCI_STOPI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/O
VDD_IOVDD_IOVDD_IOVDD_IOVDD_IOVDD_IOVDD_IOVDD_IOVDD_IOVDD_IOVDD_IOVDD_IOVDD_IOVDD_IOVDD_IOVDD_IOVDD_IO
PCIPCIPCIPCIPCIPCIPCIPCIDRV8DRV8PCIPCIPCIDRV8PCIPCIPCI
PCIPCIPCIPCIPCIPCIPCIPCITTLTTLPCIPCIPCITTLPCIPCIPCI
MPC5200 Data Sheet, Rev. 4
66
Freescale Semiconductor
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Package Description
Table52. MPC5200 Pinout Listing (continued)
Name
PCI_TRDYAlias
TypeI/O
Power SupplyVDD_IOLocal Plus
LP_ACKLP_ALELP_OELP_RWLP_TSLP_CS0LP_CS1LP_CS2LP_CS3LP_CS4LP_CS5I/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/O
VDD_IOVDD_IOVDD_IOVDD_IOVDD_IOVDD_IOVDD_IOVDD_IOVDD_IOVDD_IOVDD_IOATA
ATA_DACKATA_DRQATA_INTRQATA_IOCHRDYATA_IORATA_IOWATA_ISOLATION
I/OI/OI/OI/OI/OI/OI/O
VDD_IOVDD_IOVDD_IOVDD_IOVDD_IOVDD_IOVDD_IOEthernet
ETH_0ETH_1ETH_2ETH_3ETH_4ETH_5ETH_6ETH_7
TX, TX_ENRTS, TXD[0]USB_TXP, TX,
TXD[1]USB_PRTPWR,
TXD[2]USB_SPEED,
TXD[3]USB_SUPEND,
TX_ERUSB_OE, RTS,
MDCTXN, MDIO
I/OI/OI/OI/OI/OI/OI/OI/O
VDD_IOVDD_IOVDD_IOVDD_IOVDD_IOVDD_IOVDD_IOVDD_IO
DRV4DRV4DRV4DRV4DRV4DRV4DRV4DRV4
TTLTTLTTLTTLTTLTTLTTLTTL
DRV8DRV8DRV8DRV8DRV8DRV8DRV8
TTLTTLTTLTTLTTLTTLTTL
PULLDOWNPULLDOWNPULLUP
DRV8DRV8DRV8DRV8DRV8DRV8DRV8DRV8DRV8DRV8DRV8
TTLTTLTTLTTLTTLTTLTTLTTLTTLTTLTTL
PULLUP
Output Driver
Type
PCI
Input TypePCI
Pull-up/down
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor
67
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Package Description
Table52. MPC5200 Pinout Listing (continued)
Name
ETH_8ETH_9ETH_10ETH_11ETH_12ETH_13ETH_14ETH_15ETH_16ETH_17
AliasRX_DVCD, RX_CLKCTS, COLTX_CLKRXD[0]USB_RXD, CTS,
RXD[1]USB_RXP, UART_RX, RXD[2]USB_RXN, RX,
RXD[3]USB_OVRCNT, CTS, RX_ERCD, CRS
TypeI/OI/OI/OI/OI/OI/OI/OI/OI/OI/O
Power SupplyVDD_IOVDD_IOVDD_IOVDD_IOVDD_IOVDD_IOVDD_IOVDD_IOVDD_IOVDD_IOIRDA
PSC6_0PSC6_1PSC6_2PSC6_3
IRDA_RX, TxD
RxDFrame, CTSIR_USB_CLK,BitC
lk, RTS
I/OI/OI/OI/O
VDD_IOVDD_IOVDD_IOVDD_IOUSB
USB_0USB_1USB_2USB_3USB_4USB_5USB_6USB_7USB_8USB_9
USB_OEUSB_TXNUSB_TXPUSB_RXDUSB_RXPUSB_RXNUSB_PRTPWRUSB_SPEEDUSB_SUPENDUSB_OVRCNT
I/OI/OI/OI/OI/OI/OI/OI/OI/OI/O
VDD_IOVDD_IOVDD_IOVDD_IOVDD_IOVDD_IOVDD_IOVDD_IOVDD_IOVDD_IOI2C
I2C_0I2C_1I2C_2
SCLSDASCL
I/OI/OI/O
VDD_IOVDD_IOVDD_IO
DRV4DRV4DRV4
SchmittSchmittSchmitt
DRV4DRV4DRV4DRV4DRV4DRV4DRV4DRV4DRV4DRV4
TTLTTLTTLTTLTTLTTLTTLTTLTTLTTL
DRV4DRV4DRV4DRV4
TTLTTLTTLTTL
Output Driver
Type
DRV4DRV4DRV4DRV4DRV4DRV4DRV4DRV4DRV4DRV4
Input TypeTTLSchmittTTLSchmittTTLTTLTTLTTLTTLTTL
Pull-up/down
MPC5200 Data Sheet, Rev. 4
68
Freescale Semiconductor
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Package Description
Table52. MPC5200 Pinout Listing (continued)
Name
I2C_3
AliasSDA
TypeI/O
Power SupplyVDD_IOPSC
PSC1_0PSC1_1PSC1_2PSC1_3PSC1_4PSC2_0PSC2_1PSC2_2PSC2_3PSC2_4PSC3_0PSC3_1PSC3_2PSC3_3PSC3_4PSC3_5PSC3_6PSC3_7PSC3_8PSC3_9
TxD, Sdata_out, MOSI, TXRxD, Sdata_in, MISO, TXMclk, Sync, RTSBitClk, SCK, CTSFrame, SS, CDTxD, Sdata_out, MOSI, TXRxD, Sdata_in, MISO, TXMclk, Sync, RTSBitClk, SCK, CTSFrame, SS, CDUSB_OE, TxDS,
TXUSB_TXN, RxD,
RXUSB_TXP, BitClk,
RTSUSB_RXD, Frame,
SS, CTSUSB_RXP, CDUSB_RXNUSB_PRTPWR, Mclk, MOSIUSB_SPEED.
MISOUSB_SUPEND,
SSUSB_OVRCNT,
SCK
I/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/O
VDD_IOVDD_IOVDD_IOVDD_IOVDD_IOVDD_IOVDD_IOVDD_IOVDD_IOVDD_IOVDD_IOVDD_IOVDD_IOVDD_IOVDD_IOVDD_IOVDD_IOVDD_IOVDD_IOVDD_IOGPIO/TIMER
GPIO_WKUP_6GPIO_WKUP_7TIMER_0
MEM_CS1I/OI/OI/O
VDD_MEM_IOVDD_IOVDD_IO
DRV16_MEM
DRV8DRV4
TTLTTLTTL
PULLUP_MEM
DRV4DRV4DRV4DRV4DRV4DRV4DRV4DRV4DRV4DRV4DRV4DRV4DRV4DRV4DRV4DRV4DRV4DRV4DRV4DRV4
TTLTTLTTLTTLTTLTTLTTLTTLTTLTTLTTLTTLTTLTTLTTLTTLTTLTTLTTLTTL
Output Driver
Type
DRV4
Input TypeSchmitt
Pull-up/down
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor
69
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Package Description
Table52. MPC5200 Pinout Listing (continued)
Name
TIMER_1TIMER_2TIMER_3TIMER_4TIMER_5TIMER_6TIMER_7
MOSIMISOSSSCKAlias
TypeI/OI/OI/OI/OI/OI/OI/O
Power SupplyVDD_IOVDD_IOVDD_IOVDD_IOVDD_IOVDD_IOVDD_IOClock
SYS_XTAL_INSYS_XTAL_OUTRTC_XTAL_INRTC_XTAL_OUT
InputOutputInputOutput
VDD_IOVDD_IOVDD_IOVDD_IOMisc
PORRESETHRESETSRESETIRQ0IRQ1IRQ2IRQ3
InputI/OI/OI/OI/OI/OI/O
VDD_IOVDD_IOVDD_IOVDD_IOVDD_IOVDD_IOVDD_IO
DRV4DRV8_OD1DRV8_OD1DRV4DRV4DRV4DRV4
SchmittSchmittSchmittTTLTTLTTLTTL
Output Driver
Type
DRV4DRV4DRV4DRV4DRV4DRV4DRV4
Input TypeTTLTTLTTLTTLTTLTTLTTL
Pull-up/down
Test/Configuration
SYS_PLL_TPATEST_MODE_0TEST_MODE_1TEST_SEL_0TEST_SEL_1JTAG_TCKJTAG_TDIJTAG_TDOJTAG_TMSJTAG_TRSTTCKTDITDOTMSTRST
I/OInputInputI/OI/OInputInputI/OInputInput
VDD_IOVDD_IOVDD_IOVDD_IOVDD_IOVDD_IOVDD_IOVDD_IOVDD_IOVDD_IO
DRV4DRV4DRV4DRV4DRV8DRV4DRV4DRV8DRV4DRV4
TTLTTLTTLTTLTTLTTLTTLTTLTTLTTL
PULLUPPULLUPPULLUPPULLUPPULLUP
MPC5200 Data Sheet, Rev. 4
70
Freescale Semiconductor
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System Design Information
Table52. MPC5200 Pinout Listing (continued)
Name
Alias
Type
Power Supply
Output Driver
Type
Input Type
Pull-up/down
Power and Ground
VDD_IOVDD_MEM_IOVDD_COREVSS_IO/CORESYS_PLL_AVDDCORE_PLL_AVDD
1
------
NOTES:
All “open drain” outputs of the MPC5200 are actually regular three-state output drivers with the output data tied low and the output enable controlled. Thus, unlike a true open drain, there is a current path from the external system to the MPC5200 I/O power rail if the external signal is driven above the MPC5200 I/O power rail voltage.
5
5.1
System Design Information
Power UP/Down Sequencing
Figure52 shows situations in sequencing the I/O VDD (VDD_IO), Memory VDD (VDD_IO_MEM), PLL VDD (PLL_AVDD), and Core VDD (VDD_CORE).
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor
71
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System Design Information
DC Power Supply Voltage3.3V
VDD_IO,
VDD_IO_MEM (SDR)VDD_IO_MEM (DDR)
2.5V
1.5V
1
VDD_CORE,PLL_AVDD
2
0
Time
Note:
1.VDD_CORE should not exceed VDD_IO, VDD_IO_MEM or PLL_AVDD by more than 0.4 V at any time, including power-up.
2.It is recommended that VDD_CORE/PLL_AVDD should track VDD_IO/VDD_IO_MEM up to 0.9 V then separate for completion of ramps.
3.Input voltage must not be greater than the supply voltage (VDD_IO, VDD_IO_MEM, VDD_CORE, or PLL_AVDD) by more than 0.5 V at any time, including during power-up.4.Use 1 microsecond or slower rise time for all supplies.
Figure52. Supply Voltage Sequencing
The relationship between VDD_IO_MEM and VDD_IO is non-critical during power-up and power-down sequences. Both VDD_IO_MEM (2.5 V or 3.3 V) and VDD_IO are specified relative to VDD_CORE.
5.1.1Power Up Sequence
If VDD_IO/VDD_IO_MEM are powered up with the VDD_CORE at 0V, the sense circuits in the I/O pads will cause all pad output drivers connected to the VDD_IO/VDD_IO_MEM to be in a high-impedance state. There is no limit to how long after VDD_IO/VDD_IO_MEM powers up before VDD_CORE must power up. VDD_CORE should not lead the VDD_IO, VDD_IO_MEM or PLL_AVDD by more than 0.4 V during power ramp up or there will be high current in the internal ESD protection diodes. The rise times on the power supplies should be slower than 1 microsecond to avoid turning on the internal ESD protection clamp diodes.
The recommended power up sequence is as follows:Use one microsecond or slower rise time for all supplies.
MPC5200 Data Sheet, Rev. 4
72
Freescale Semiconductor
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System Design Information
VDD_CORE/PLL_AVDD and VDD_IO/VDD_IO_MEM should track up to 0.9 V and then separate for the completion of ramps with VDD_IO/VDD_IO_MEM going to the higher external voltages. One way to accomplish this is to use a low drop-out voltage regulator.
5.1.2Power Down Sequence
If VDD_CORE/PLL_AVDD are powered down first, then sense circuits in the I/O pads will cause all output drivers to be in a high impedance state. There is no limit on how long after VDD_CORE and PLL_AVDD power down before VDD_IO or VDD_IO_MEM must power down. VDD_CORE should not lag VDD_IO, VDD_IO_MEM, or PLL_AVDD going low by more than 0.4V during power down or there will be undesired high current in the ESD protection diodes. There are no requirements for the fall times of the power supplies.
The recommended power down sequence is as follows:
Drop VDD_CORE/PLL_AVDD to 0V.Drop VDD_IO/VDD_IO_MEM supplies.
5.2System and CPU Core AVDD power supply filtering
Each of the independent PLL power supplies require filtering external to the device. The following drawing is a recommendation for the required filter circuit.
PowerSupplysource
10 Ω
< 1 Ω
AVDD device pin
200-400 pF
10 µF
Figure53. Power Supply Filtering
5.3
5.3.1
Pull-up/Pull-down Resistor Requirements
Pull-down Resistor Requirements for TEST pins
The MPC5200 requires external pull-up or pull-down resistors on certain pins.
The MPC5200 requires pull-down resistors on the test pins TEST_MODE_0, TEST_MODE_1, TEST_SEL_1.
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor
73
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System Design Information
5.3.2Pull-up Requirements for the PCI Control Lines
If the PCI interface is NOT used (and internally disabled) the PCI control pins must be terminated as indicated by the PCI Local Bus specification [4]. This is also required for MOST/Graphics and Large Flash Mode.
PCI control signals always require pull-up resistors on the motherboard (not the expansion board) to ensure that they contain stable values when no agent is actively driving the bus. This includes PCI_FRAME, PCI_TRDY, PCI_IRDY, PCI_DEVSEL, PCI_STOP, PCI_SERR, PCI_PERR, and PCI_REQ.
5.3.3
Pull-up/Pull-down Requirements for MEM_MDQS pins (SDRAM)
The MEM_MDQS[3:0] signals are not used with SDR memories and require pull-up or pull-down resistors in SDRAM mode.
5.4JTAG
The MPC5200 provides the user an IEEE 1149.1 JTAG interface to facilitate board/system testing. It also provides a Common On-Chip Processor (COP) Interface, which shares the IEEE 1149.1 JTAG port. The COP Interface provides access to the MPC5200's imbedded Freescale (formerly Motorola) MPC603e G2_LE processor. This interface provides a means for executing test routines and for performing software development & debug functions.
5.4.1JTAG_TRST
Boundary scan testing is enabled through the JTAG interface signals. The JTAG_TRST signal is optional in the IEEE 1149.1 specification but is provided on all processors that implement the PowerPC
architecture. To obtain a reliable power-on reset performance, the JTAG_TRST signal must be asserted during power-on reset.
5.4.1.1JTAG_TRST and PORRESET
The JTAG interface can control the direction of the MPC5200 I/O pads via the boundary scan chain. The JTAG module must be reset before the MPC5200 comes out of power-on reset; do this by asserting JTAG_TRST before PORRESET is released.
For more details refer to the Reset and JTAG Timing Specification.
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System Design Information
PORRESET
required assertion of JTAG_TRST
optional assertion of JTAG_TRST
JTAG_TRST
Figure. PORRESET vs. JTAG_TRST 5.4.1.2Connecting JTAG_TRST
The wiring of the JTAG_TRST depends on the existence of a board-related debug interface (see Table 53 below).
Normally this interface is implemented, using a COP (common on-chip processor) connector. The COP allows a remote computer system (typically, a PC with dedicated hardware and debugging software) to access and control the internal operations of the MPC5200.
5.4.2G2_LE COP/BDM Interface
There are two possibilities to connect the JTAG interface: using it with a COP connector and without a COP connector.
5.4.2.1Boards interfacing the JTAG port via a COP connector
The MPC5200 functional pin interface and internal logic provides access to the embedded G2_LE
processor core through the Freescale (formerly Motorola) standard COP/BDM interface. Table53 gives the COP/BDM interface signals. The pin order shown reflects only the COP/BDM connector order.
Table53. COP/BDM Interface Signals
BDMPin #161514131211109
MPC5200I/O Pin
—TEST_SEL_0
—HRESET—SRESET—JTAG_TMS
BDMConnectorGNDckstp_outKEYhresetGNDsresetN/Ctms
—100k Pull-Up
—InternalPullUp/Down
———
ExternalPullUp/Down
———10k Pull-Up
—10k Pull-Up
—10k Pull-Up
I/O1—I—O—O—O
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System Design Information
Table53. COP/BDM Interface Signals (continued)
BDMPin #876321
1
MPC5200I/O Pin
—JTAG_TCK
—
See Note 3.
JTAG_TRSTJTAG_TDISee Note 4.
JTAG_TDO
BDMConnector
N/CtckVDD2halted3trsttdiqack4tdo
InternalPullUp/Down
—100k Pull-Up
——100k Pull-Up100k Pull-Up
——
ExternalPullUp/Down
—10k Pull-Up
——10k Pull-Up10k Pull-Up
——
I/O1—O—IOOOI
NOTES:
With respect to the emulator tool’s perspective:
Input is really an output from the embedded G2_LE core.Output is really an input to the core.
2From the board under test, power sense for chip power.3HALTED is not available from G2_LE core.
4Input to the G2_LE core to enable/disable soft-stop condition during breakpoints. MPC5200 internal ties core_qack_ to GND in its normal/functional mode (always asserted).
For a board with a COP (common on-chip processor) connector, which accesses the JTAG interface and which needs to reset the JTAG module, simply wiring JTAG_TRST and PORRESET is not recommended.To reset the MPC5200 via the COP connector, the HRESET pin of the COP should be connected to the HRESET pin of the MPC5200. The circuitry shown in Figure55 allows the COP to assert HRESET or JTAG_TRST separately, while any other board sources can drive PORRESET.MPC5200 Data Sheet, Rev. 4
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System Design Information
PORRESETPORRESET10KohmHRESETVDDVDD10Kohm10KohmTRSTJTAG_TRSTTMS10KohmVDDJTAG_TMSTCKVDDTDI10KohmVDDJTAG_TDI1515324108CKSTP_OUTTDOhaltedqackNCNCNCNCTEST_SEL_0JTAG_TDO10KohmVDDJTAG_TCKSRESETVDD4Key 14912MPC5200
COP Header131116HRESETSRESETCOP ConnectorPhysical Pinout1357911131524681012K16Key7623Figure55. COP Connector Diagram
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System Design Information
5.4.2.2Boards without COP connector
If the JTAG interface is not used, JTAG_TRST should be tied to PORRESET, so that it is asserted when the system reset signal (PORRESET) is asserted. This ensures that the JTAG scan chain is initialized during power on. Figure56 shows the connection of the JTAG interface without COP connector.
PORRESETPORRESET10Kohm10KohmHRESETVDDVDDSRESETMPC5200
HRESETSRESETJTAG_TRST10KohmVDDJTAG_TMS10KohmVDDJTAG_TCK10KohmVDDJTAG_TDITEST_SEL_0JTAG_TDOFigure56. JTAG_TRST wiring for boards without COP connectorMPC5200 Data Sheet, Rev. 4
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Ordering Information
6Ordering Information
Table. Ordering Information
Part NumberMPC5200BV400MPC5200CBV266MPC5200CBV400SPC5200CBV400
Speed4002600400
Ambient Temp0C to 70C-40C to 85C-40C to 85C-40C to 85C
QualificationCommercialIndustrialIndustrialAutomotive - AEC
7Document Revision History
Table55. Document Revision History
Rev. No.0.10.20.2.10.31.02.03.04.0
Substantive Change(s)
First Preliminary release with some TBD’s in spec tables (6/2003)
Added AC specs for missing modules, power-on sequence, misc other updates (7/2003)Corrected maximum core operating frequency (7/2003)
Added Memory Interface Timing values, misc other updates (8/2003)Added Information about JTAG_TRST (11/2003)
Added Power Numbers (Section 3.1.5), updated Oscillator and PLL Characteristics (Section 3.2), updated SDRAM AC Characteristics (Section 3.3.5)Change to Freescale brand and format (8/2004)
Updates to LPC timing, DDR SDRAM timing, JTAG section, replaced TBD’s (1/2005)
Rev 4 has been regenerated with the new Freescale appearance guidelines, the title was changed and the reference to www.mobilegt.com in the first paragraph (Note) was changed to www. freescale.com (3/2006).
Table55 provides a revision history for this hardware specification.
For more detailed information, refer to the following documentation:[1]MPC5200 User Manual MPC5200UM[2][3][4][5][6]
PowerPC Microprocessor Family: The Programming Environments for 32-bit Microprocessors, Rev. 2: MPCFPE32B/AD
G2 Core Reference Manual, Rev. 0: G2CORERM/D
PCI Local Bus Specification, Revision 2.2, December 18, 1998 ANSI ATA-4 Specification
IEEE 802.3 Specification (ETHERNET)
MPC5200 Data Sheet, Rev. 4
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unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale
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