KK74HCT139AD资料

TECHNICAL DATA

KK74HCT139A

Dual 1-of-4 Decoder/Demultiplexer

High-Performance Silicon-Gate CMOS

The KK74HCT139A is identical in pinout to the LS/ALS139. The KK74HCT139A may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs.

This device consists of two independent 1-of-4 decoders, each of which decodes a two-bit Address to one-of-four active-low outputs. Active-low Selects are provided to facilitate the demultiplexing and cascading functions. The demultiplexing function is accomplished by using the Address inputs to select the desired device output, and utilizing

the Select as a data input.

ORDERING INFORMATION • TTL/NMOS Compatible Input Levels

KK74HCT139AN Plastic • Outputs Directly Interface to CMOS, NMOS, and TTL KK74HCT139AD SOIC • Operating Voltage Range: 4.5 to 5.5 V TA = -55° to 125° C for all packages • Low Input Current: 1.0 µA PIN ASSIGNMENT

LOGIC DIAGRAM

FUNCTION TABLE

Inputs Outputs

PIN 16 =VCC

PIN 8 = GND

Select A1 A0Y0 Y1 Y2 Y3

H X X H H H H L L L L H H H L L H H L H H L H L H H L H L H H H H H L X = don’t care

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KK74HCT139A

MAXIMUM RATINGS*

Symbol Parameter VCCVINVOUTIINIOUTICCPDTstg TL

*

Value Unit -0.5 to +7.0 -1.5 to VCC +1.5 -0.5 to VCC +0.5

±20 ±25 ±50 750 500 -65 to +150

260

V V V mA mA mA mW °C °C

DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Current, per Pin

DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Storage Temperature

Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package)

Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C

SOIC Package: : - 7 mW/°C from 65° to 125°C

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min Max Unit VCCVIN, VOUT

TAtr, tf

This device contains protection circuitry to guard against damage due to high static voltages or electric fields.

However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused

outputs must be left open.

DC Supply Voltage (Referenced to GND)

DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1)

4.5 0 -55 0

5.5 VCC+125 500

V V °C ns

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KK74HCT139A

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

VCC

Guaranteed Limit

≤85 °C 2.0 2.0 0.8 0.8 4.4 5.4 3.84 0.1 0.1 0.33 ±1.0

≤125 °C 2.0 2.0 0.8 0.8 4.4 5.4 3.7 0.1 0.1 0.4 ±1.0

Unit

Symbol Parameter Test Conditions V 25 °C

to -55°C

4.55.54.55.54.55.5 4.54.55.5 4.55.55.5

2.0 2.0 0.8 0.8 4.4 5.4 3.98 0.1 0.1 0.26 ±0.1

VIHVILVOH VOL IINICC

Minimum High-Level Input Voltage Maximum Low -Level Input Voltage

VOUT=0.1 V or VCC-0.1 V ⎢IOUT⎢≤ 20 µA

VOUT=0.1 V or VCC-0.1 V ⎢IOUT⎢ ≤ 20 µA

V V V V µA

Minimum High-VIN=VIH or VIL

Level Output Voltage ⎢IOUT⎢ ≤ 20 µA

VIN=VIH or VIL ⎢IOUT⎢ ≤ 4.0 mA

Maximum Low-VIN=VIH or VIL

Level Output Voltage ⎢IOUT⎢ ≤ 20 µA

Maximum Input Leakage Current Maximum Quiescent Supply Current (per Package) Additional Quiescent Supply Current

VIN=VIH or VIL ⎢IOUT⎢ ≤ 4.0 mA VIN=VCC or GND VIN=VCC or GND IOUT=0µA

VIN = 2.4 V, Any One Input VIN=VCC or GND, Other Inputs IOUT=0µA

4.0 40 160 µA

∆ICC

≥-55°C 25°C to

125°C

mA

5.52.9 2.4

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KK74HCT139A

AC ELECTRICAL CHARACTERISTICS (VCC=5.0 V ± 10%, CL=50pF,Input tr=tf=6.0 ns)

Symbol Parameter 25 °C

to -55°CtPLH, tPHLtPLH, tPHLtTLH, tTHL

CIN

CPD

Power Dissipation Capacitance (Per Decoder) Used to determine the no-load dynamic power consumption:

PD=CPDVCC2f+ICCVCC

Typical @25°C,VCC=5.0 V

60 pF Maximum Propagation Delay, Select to OutputY (Figures 1 and 3)

Maximum Propagation Delay , Input A to OutputY (Figures 2 and 3)

Maximum Output Transition Time, Any Output (Figures 1 and 3)

Maximum Input Capacitance

≤85°C

≤125°C

Unit

Guaranteed Limit 23 29 35 ns 23 29 35 ns 15 19 22 ns 10

10

10

pF

Figure 1. Switching Waveforms Figure 2. Switching Waveforms

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KK74HCT139A

Figure 3. Test Circuit

EXPANDED LOGIC DIAGRAM

(1/2 of Device)

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KK74HCT139A

N SUFFIX PLASTIC DIP(MS - 001BB)ADimension, mm169B18SymbolABCMIN18.676.1MAX19.697.115.33FLDF0.361.142.547.620°2.927.620.20.380.561.78C-T-SEATINGNGD0.25 (0.010) M TKPLANEGHHJMJKLMN10°3.818.260.36NOTES:1. Dimensions “A”, “B” do not include mold flash or protrusions. Maximum mold flash or protrusions 0.25 mm (0.010) per side.D SUFFIX SOIC(MS - 012AC)Dimension, mmA169SymbolAMIN9.83.81.350.330.41.275.720°0.10.195.80.25MAX1041.750.511.27HBPBC1G8CR x 45DFGJFM-T-D0.25 (0.010) M TCMKSEATINGPLANEHJKMPR8°0.250.256.20.5NOTES:1. Dimensions A and B do not include mold flash or protrusion.2. Maximum mold flash or protrusion 0.15 mm (0.006) per side for A; for B ‑ 0.25 mm (0.010) per side.

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