专利名称：Voltage subtractor for serial-parallel
analog-to-digital converter
发明人：Stephen J. Kreinick,Fuad H. Musa,Pern Shaw申请号：US05/7491申请日：19770131公开号：US04124824A公开日：19781107
摘要：A high-speed voltage subtractor circuit suitable for use in a serial- parallel A/Dconverter uses differential current switches to select a predetermined reference voltagevalue as one input to a precision current matching circuit whose other input is an appliedanalog input signal. An output buffer circuit coupled to the current matching circuitproduces an output signal equal to the difference between the analog input signal andthe reference voltage value.
申请人：MOTOROLA, INC.
代理人：Anthony J. Sarli, Jr.
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