Method of fabricating an integrated circuit having

专利名称：Method of fabricating an integrated circuit

having a strain inducing hollow trenchisolation region

发明人：Barry Dove申请号：US12963474申请日：20101208公开号：US08609508B2公开日：20131217

专利附图：

摘要：A shallow trench isolation is formed in a semiconductor substrate adjacent aMOS transistor. The shallow trench is filled with a fill material while other processing

steps are performed. The fill material is later removed through a thin well etched intolayers above the trench, leaving the trench hollow. A thin strain inducing layer is thenformed on the sidewall of the hollow trench. The well is then plugged, leaving the trenchsubstantially hollow except for the thin strain inducing layer on the sidewall of thetrench. The strain inducing layer is configured to induce compressive or tensile strain on achannel region of the MOS transistor and thereby to enhance conduction properties ofthe transistor.

申请人：Barry Dove

地址：Coppell TX US

国籍：US

代理机构：Seed IP Law Group PLLC

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