Method and device for circuit verification

专利名称：Method and device for circuit verification发明人：Holger Busch申请号：US10901558申请日：20040729

公开号：US20050044516A1公开日：20050224

专利附图：

摘要：When designing digital circuits, the specification of the circuit is used to

formulate properties and to check the applicability thereof using a model of the circuit. Averifier is employed and uses the model to determine whether a property is applicableby seeking a counterexample to which the property does not apply. Any counterexample

appearing is evaluated to determine whether it is caused by a defective model orwhether it should have been avoided by reformulating the property within the scope ofthe specification. Which exact part of the property led to the counterexample isdetermined when one appears. If a plurality of times is possible for a part of theproperty, the instant(s) at which specific events in the parts of the property lead to thecounterexample is determined. A developer can evaluate the counterexample muchmore quickly using this information, so the development process can be accelerated.

申请人：Holger Busch

地址：Brunnthal-Otterloh DE

国籍：DE

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