Delay time adjusting method, circuit, and system

专利名称：Delay time adjusting method, circuit, and

system

发明人：Sakata, Takashi,Hanabata, Toshio,Fujimoto,

Naonobu,Murase, Tetsuro,Ikawa, Fumihiro

申请号：EP86112327.1申请日：19860904公开号：EP0213641A3公开日：19890503

专利附图：

摘要：In a delay time adjusting circuit, a transmitter device divides original data into afirst data signal and a second data signal and sends the first data signal and the second

data signal via different transmission paths to a receiving device, and the receiving devicemixes the first data signal and the second data signal so as to reproduce the originaldata. In the receiving device, the first data signal is written in first elastic memory (101)and is operated in response to a clock of the first data signal, the second data signal isdelayed and corresponding bits of the first elastic memory (101) are sequentially readout in response to an output of a ring counter (104) having the same number of bits asthat of the first elastic memory (101) and operated in response to a clock of the secondsignal, and to which the position of the first data signal in the first elastic memory (101) isloaded in response to the delayed second data signal.

申请人：FUJITSU LIMITED

地址：1015, Kamikodanaka, Nakahara-ku Kawasaki-shi, Kanagawa 211 JP

国籍：JP

代理机构：Lehn, Werner, Dipl.-Ing.

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