Circuit for detecting synchronizing signal in fram

专利名称：Circuit for detecting synchronizing signal in

frame synchronization data transmission

发明人：Uomoto, Yasutomo申请号：EP98201740.2申请日：19920828公开号：EP0880248A1公开日：19981125

专利附图：

摘要：A circuit for detecting a subframe synchronizing signal in a frame

synchronization data transmission system, in which the frame is made up of a plurality ofsubframes, each subframe has M bits, and each bit is transmitted in synchronization with aclock pulse signal for data transmission, a frame synchronizing signal being assigned toall bits of a starting subframe and a subframe synchronizing signal being assigned to thekth bit of each subframe, except for the starting subframe, and the kth bit being

designated with a first logic level, the circuit including starting subframe detecting means(20) both for detecting the starting subframe and for delaying a supplied data signal byM clock-pulse periods, the starting subframe detecting means (20) generating a single-

pulse signal of the first logic level in synchronization with the kth bit of the secondsubframe that follows the starting subframe when the starting subframe detectingmeans (20) does not detect any error in the frame synchronizing signal assigned to thestarting subframe, window pulse generating means (21) for generating window pulses,the window pulses being a pulse train with a component pulse generated synchronouslywith the subframe synchronizing signal of each subframe, except for the secondsubframe, the leading pulse of the pulse train being generated by delaying the single-pulse signal by M clock-pulse periods, the subsequent pulses thereof being recursivelygenerated by delaying the preceding pulse by M clock-pulse periods, and a pulse of therecursively generated pulses that is synchronous with the single-pulse signal beingexcluded from being output, transmission gate means (22) which selects the kth bit of thesubframe, except for the starting subframe, from the data signal delayed by the startingsubframe detecting means (20) under the control of the window pulses, and errordetecting gate means (23) which selects from the output of the transmission gate means(22) any error bit of the subframe synchronizing signals.

申请人：NEC CORPORATION

地址：7-1, Shiba 5-chome Minato-ku Tokyo JP

国籍：JP

代理机构：Orchard, Oliver John

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