Am29LV800B(英文pdf)

Am29LV800B

8 Megabit (1 M x 8-Bit/512 K x 16-Bit)

CMOS 3.0 Volt-only Boot Sector Flash Memory

DISTINCTIVE CHARACTERISTICS

sSingle power supply operation

—2.7 to 3.6 volt read and write operations for battery-powered applicationssManufactured on 0.32 µm process technology—Compatible with 0.5 µm Am29LV800 devicesHigh performance

—Access times as fast as 70 ns

sUltra low power consumption (typical values at 5MHz)—200 nA Automatic Sleep mode current—200 nA standby mode current—7 mA read current

—15 mA program/erase currentsFlexible sector architecture

—One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and fifteen 64 Kbyte sectors (byte mode)—One 8 Kword, two 4 Kword, one 16 Kword, and fifteen 32 Kword sectors (word mode)—Supports full chip erase—Sector Protection features:

A hardware method of locking a sector to prevent any program or erase operations within that sectorSectors can be locked in-system or via programming equipment

Temporary Sector Unprotect feature allows code changes in previously locked sectorssUnlock Bypass Program Command

—Reduces overall programming time when issuing multiple program command sequencessTop or bottom boot block configurations available

sEmbedded Algorithms

—Embedded Erase algorithm automatically

preprograms and erases the entire chip or any combination of designated sectors—Embedded Program algorithm automatically writes and verifies data at specified addressessMinimum 1 million write cycle guarantee persectors20-year data retention at 125°C

—Reliable operation for the life of the systemsPackage option—48-ball FBGA—48-pin TSOP—44-pin SO

—Known Good Die (KGD)

(see publication number 21536)sCompatibility with JEDEC standards—Pinout and software compatible with single-power supply Flash—Superior inadvertent write protectionsData# Polling and toggle bits

—Provides a software method of detecting program or erase operation completionsReady/Busy# pin (RY/BY#)

—Provides a hardware method of detecting program or erase cycle completionsErase Suspend/Erase Resume

—Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operationsHardware reset pin (RESET#)

—Hardware method to reset the device to reading array data

This Data Sheet states AMD’s current technical specifications regarding the Product described herein. This DataSheet may be revised by subsequent versions or modifications due to changes in technical specifications.

Publication# 21490Rev: GAmendment/+2Issue Date: August 14, 2000

GENERAL DESCRIPTION

The Am29LV800B is an 8 Mbit, 3.0 volt-only Flashmemory organized as 1,048,576 bytes or 524,288words. The device is offered in 48-ball FBGA, 44-pinSO, and 48-pin TSOP packages. The device is alsoavailable in Known Good Die (KGD) form. For moreinformation, refer to publication number 21536. Theword-wide data (x16) appears on DQ15–DQ0; thebyte-wide (x8) data appears on DQ7–DQ0. This devicerequires only a single, 3.0 volt VCC supply to performread, program, and erase operations. A standardEPROM programmer can also be used to program anderase the device.

This device is manufactured using AMD’s 0.32 µmprocess technology, and offers all the features and ben-efits of the Am29LV800, which was manufactured using0.5 µm process technology. In addition, theAm29LV800B features unlock bypass programmingand in-system sector protection/unprotection.

The standard device offers access times of 70, 90, and120 ns, allowing high speed microprocessors tooperate without wait states. To eliminate bus contentionthe device has separate chip enable (CE#), writeenable (WE#) and output enable (OE#) controls.The device requires only a single 3.0 volt power sup-ply for both read and write functions. Internally gener-ated and regulated voltages are provided for theprogram and erase operations.

The device is entirely command set compatible with theJEDEC single-power-supply Flash standard. Com-mands are written to the command register using stan-dard microprocessor write timings. Register contentsserve as input to an internal state-machine that con-trols the erase and programming circuitry. Write cyclesalso internally latch addresses and data needed for theprogramming and erase operations. Reading data outof the device is similar to reading from other Flash orEPROM devices.

Device programming occurs by executing the programcommand sequence. This initiates the EmbeddedProgram algorithm—an internal algorithm that auto-matically times the program pulse widths and verifiesproper cell margin. The Unlock Bypass mode facili-tates faster programming times by requiring only twowrite cycles to program data instead of four.

Device erasure occurs by executing the erase commandsequence. This initiates the Embedded Erase

algorithm—an internal algorithm that automaticallypreprograms the array (if it is not already programmed)before executing the erase operation. During erase, thedevice automatically times the erase pulse widths andverifies proper cell margin.

The host system can detect whether a program orerase operation is complete by observing the RY/BY#pin, or by reading the DQ7 (Data# Polling) and DQ6(toggle) status bits. After a program or erase cycle hasbeen completed, the device is ready to read array dataor accept another command.

The sector erase architecture allows memory sectorsto be erased and reprogrammed without affecting thedata contents of other sectors. The device is fullyerased when shipped from the factory.

Hardware data protection measures include a lowVCC detector that automatically inhibits write opera-tions during power transitions. The hardware sectorprotection feature disables both program and eraseoperations in any combination of the sectors of mem-ory. This can be achieved in-system or via program-ming equipment.

The Erase Suspend feature enables the user to puterase on hold for any period of time to read data from,or program data to, any sector that is not selected forerasure. True background erase can thus be achieved.The hardware RESET# pin terminates any operationin progress and resets the internal state machine toreading array data. The RESET# pin may be tied to thesystem reset circuitry. A system reset would thus alsoreset the device, enabling the system microprocessorto read the boot-up firmware from the Flash memory.The device offers two power-saving features. When ad-dresses have been stable for a specified amount oftime, the device enters the automatic sleep mode.The system can also place the device into the standbymode. Power consumption is greatly reduced in boththese modes.

AMD’s Flash technology combines years of Flashmemory manufacturing experience to produce thehighest levels of quality, reliability and cost effective-ness. The device electrically erases all bits withina sector simultaneously via Fowler-Nordheim tun-neling. The data is programmed using hot electron injec-tion.

2Am29LV800B

TABLE OF CONTENTS

Product Selector Guide . . . . . . . . . . . . . . . . . . . . .4Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . .5Special Handling Instructions for FBGA Package ..7Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . 7Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Ordering Information . . . . . . . . . . . . . . . . . . . . . . .8Standard Products ..................................................8Device Bus Operations . . . . . . . . . . . . . . . . . . . . . .9

Table 1. Am29LV800B Device Bus Operations ............9

CMOS Compatible ...............................................25

Figure 9. ICC1 Current vs. Time (Showing Active and AutomaticSleepCurrents).......................................... 26Figure 10. Typical ICC1 vs. Frequency........................ 26

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 11. Test Setup.................................................. 27Table 7. Test Specifications ........................................27

Key to Switching Waveforms. . . . . . . . . . . . . . . . 27

Figure 12. Input Waveforms and

MeasurementLevels................................................... 27

Word/Byte Configuration ........................................9Requirements for Reading Array Data ...................9Writing Commands/Command Sequences ............9Program and Erase Operation Status ..................10Standby Mode ......................................................10Automatic Sleep Mode .........................................10RESET#: Hardware Reset Pin .............................10Output Disable Mode ............................................11

Table 2. Am29LV800BT Top Boot Block

SectorAddresses ........................................................11Table 3. Am29LV800BB Bottom Boot Block

SectorAddresses ........................................................12

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 28Read Operations ..................................................28

Figure 13. Read Operations Timings.......................... 28

Hardware Reset (RESET#) ..................................29

Figure 14. RESET# Timings........................................ 29

Word/Byte Configuration (BYTE#) .....................30

Figure 15. BYTE# Timings for Read Operations......... 30Figure 16. BYTE# Timings for Write Operations......... 30

Erase/Program Operations ...................................31

Figure 17. Program Operation Timings....................... 32Figure 18. Chip/Sector Erase Operation Timings........ 33Figure 19. Data# Polling Timings (During

EmbeddedAlgorithms)................................................ 34Figure 20. Toggle Bit Timings (During

EmbeddedAlgorithms)................................................ 34Figure 21. DQ2 vs. DQ6.............................................. 35

Autoselect Mode ...................................................12

Table 4. Am29LV800B Autoselect Codes

(HighVoltageMethod) ................................................13

Sector Protection/Unprotection ............................13Temporary Sector Unprotect ................................13

Figure 1. Temporary Sector Unprotect Operation....... 13Figure 2. In-System Sector Protect/

Sector Unprotect Algorithms....................................... 14

Temporary Sector Unprotect ................................35

Figure 22. Temporary Sector Unprotect

TimingDiagram........................................................... 35Figure 23. Sector Protect/Unprotect

TimingDiagram........................................................... 36

Hardware Data Protection ....................................15Command Definitions . . . . . . . . . . . . . . . . . . . . . 15Reading Array Data ..............................................15Reset Command ..................................................15Autoselect Command Sequence ..........................15Word/Byte Program Command Sequence ...........16

Figure 3. Program Operation...................................... 17

Alternate CE# Controlled

Erase/Program Operations ...................................37

Figure 24. Alternate CE# Controlled Write

OperationTimings....................................................... 38

Chip Erase Command Sequence .........................17Sector Erase Command Sequence ......................17Erase Suspend/Erase Resume Commands .........18

Figure 4. Erase Operation........................................... 18Table 5. Am29LV800B Command Definitions .............19

Write Operation Status . . . . . . . . . . . . . . . . . . . . 20DQ7: Data# Polling ...............................................20

Figure 5. Data# Polling Algorithm............................... 20

RY/BY#: Ready/Busy# .........................................21DQ6: Toggle Bit I ..................................................21DQ2: Toggle Bit II .................................................21Reading Toggle Bits DQ6/DQ2 ............................21DQ5: Exceeded Timing Limits ..............................22DQ3: Sector Erase Timer .....................................22

Figure 6. Toggle Bit Algorithm..................................... 22Table 6. Write Operation Status ..................................23

Absolute Maximum Ratings . . . . . . . . . . . . . . . . .24Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 24DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . .25

Erase and Programming Performance . . . . . . . 39Latchup Characteristics. . . . . . . . . . . . . . . . . . . . 39TSOP and SO Pin Capacitance . . . . . . . . . . . . . . 39Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 39Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 40TS 048—48-Pin Standard TSOP ........................40TSR048—48-Pin Reverse TSOP ........................41FBB 048—48-Ball Fine-Pitch Ball Grid Array (FBGA)6x9mm ................................................42SO 044—44-Pin Small Outline Package .............43Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 44Revision E (January 1998) ...................................44Revision E+1 (March 1998) ..................................44Revision F (January 1999) ...................................44Revision F+1 (February 1999) .............................44Revision F+2 (February 1999) .............................44Revision F+3 (July 2, 1999) .................................44Revision F+4 (July 26, 1999) ...............................44Revision G (November 10, 1999) .........................45Revision G+1 (July 7, 2000) .................................45Revision G+2 (August 14, 2000) ..........................45

Am29LV800B3

PRODUCT SELECTOR GUIDE

Family Part NumberSpeed Options

Full Voltage Range: VCC = 2.7–3.6 V

-70707030

Am29LV800B

-90909035

-12012012050

Max access time, ns (tACC)Max CE# access time, ns (tCE)Max OE# access time, ns (tOE)

Note: See “AC Characteristics” for full specifications.BLOCK DIAGRAM

RY/BY#

VCCVSSRESET#

Sector SwitchesErase VoltageGenerator

Input/OutputBuffersDQ0–DQ15 (A-1)

WE#BYTE#

StateControlCommandRegister

PGM VoltageGenerator

Chip EnableOutput Enable

Logic

STB

DataLatch

CE#OE#

STB

VCC Detector

Timer

Address LatchY-DecoderY-Gating

X-Decoder

Cell Matrix

A0–A18

4Am29LV800B

CONNECTION DIAGRAMS

This device is also available in Known Good Die (KGD) form. Refer to publication number 21536 formoreinformation.

A15A14A13A12A11A10A9A8NCNCWE#RESET#NCNCRY/BY#A18A17A7A6A5A4A3A2A1123456789101112131415161718192021222324484746454443424140393837363534333231302928272625A16BYTE#VSSDQ15/A-1DQ7DQ14DQ6DQ13DQ5DQ12DQ4VCCDQ11DQ3DQ10DQ2DQ9DQ1DQ8DQ0OE#VSSCE#A0Standard TSOPA16BYTE#VSSDQ15/A-1DQ7DQ14DQ6DQ13DQ5DQ12DQ4VCCDQ11DQ3DQ10DQ2DQ9DQ1DQ8DQ0OE#VSSCE#A0123456789101112131415161718192021222324Reverse TSOP484746454443424140393837363534333231302928272625A15A14A13A12A11A10A9A8NCNCWE#RESET#NCNCRY/BY#A18A17A7A6A5A4A3A2A121490G-2

Am29LV800B5

CONNECTION DIAGRAMS

This device is also available in Known Good Die (KGD) form. Refer to publication number 21536 formoreinformation.

RY/BY#A18A17A7A6A5A4A3A2A1A0CE#VSSOE#DQ0DQ8DQ1DQ9DQ2DQ10DQ3DQ1112345678910111213141516171819202122SO44434241403938373635343332313029282726252423RESET#WE#A8A9A10A11A12A13A14A15A16BYTE#VSSDQ15/A-1DQ7DQ14DQ6DQ13DQ5DQ12DQ4VCCFBGATop View, Balls Facing DownA6A13A5A9A4WE#A3RY/BY#A2A7A1A3B6A12B5A8B4RESET#B3NCB2A17B1A4C6A14C5A10C4NCC3A18C2A6C1A2D6A15D5A11D4NCD3NCD2A5D1A1E6A16E5DQ7E4DQ5E3DQ2E2DQ0E1A0F6G6H6VSSH5DQ6H4DQ4H3DQ3H2DQ1H1VSSBYTE#DQ15/A-1F5DQ14F4DQ12F3DQ10F2DQ8F1CE#G5DQ13G4VCCG3DQ11G2DQ9G1OE#6Am29LV800B

Special Handling Instructions for FBGA Package

Special handling is required for Flash Memory productsin FBGA packages.

Flash memory devices in FBGA packages may bedamaged if exposed to ultrasonic cleaning methods.The package and/or data integrity may becompromised if the package body is exposed totemperatures above 150°C for prolonged periods oftime.

PIN CONFIGURATION

A0–A18

=19 addresses

DQ0–DQ14=15 data inputs/outputsDQ15/A-1BYTE#CE#OE#WE#RESET#RY/BY#VCC

=DQ15 (data input/output, word mode),

A-1 (LSB address input, byte mode)=Selects 8-bit or 16-bit mode=Chip enable= Output enable=Write enable

=Hardware reset pin, active low= Ready/Busy# output

=3.0 volt-only single power supply

(see Product Selector Guide for speedoptions and voltage supply tolerances)=Device ground

=Pin not connected internally

LOGIC SYMBOL

19

A0–A18

DQ0–DQ15

(A-1)

CE#OE#WE#RESET#BYTE#

RY/BY#

16 or 8

VSSNC

Am29LV800B7

ORDERING INFORMATIONStandard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combi-nation) is formed by a combination of the elements below.

Am29LV800B

T

-70

E

C

TEMPERATURE RANGEC=Commercial (0°C to +70°C)I = Industrial (–40°C to +85°C)E =Extended (–55°C to +125°C)

PACKAGE TYPEE=48-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 048)F=48-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR048)S=44-Pin Small Outline Package (SO 044)WB=48-Ball Fine Pitch Ball Grid Array (FBGA)

0.80 mm pitch, 6 x 9 mm package (FBB048)

This device is also available in Known Good Die (KGD) form. See publication number 21536 for more information.

SPEED OPTION

See Product Selector Guide and Valid CombinationsBOOT CODE SECTOR ARCHITECTURET= Top sectorB= Bottom sector

DEVICE NUMBER/DESCRIPTION

Am29LV800B

8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS Flash Memory3.0 Volt-only Read, Program, and Erase

Valid Combinations for TSOP and SO PackagesAM29LV800BT-70,AM29LV800BB-70AM29LV800BT-90,AM29LV800BB-90AM29LV800BT-120,AM29LV800BB-120

EC, EI, FC, FI, SC, SI

Valid Combinations for FBGA PackagesOrder Number

AM29LV800BT-70,AM29LV800BB-70AM29LV800BT-90,AM29LV800BB-90AM29LV800BT-120,AM29LV800BB-120

Package MarkingL800BT70V,L800BB70V

WBC, L800BT90V,WBIL800BB90V

L800BT12V,L800BB12V

C, I

EC, EI, EE, FC, FI, FE,SC, SI, SE

Valid Combinations

Valid Combinations list configurations planned to be sup-ported in volume for this device. Consult the local AMD salesoffice to confirm availability of specific valid combinations andto check on newly released combinations.

8Am29LV800B

DEVICE BUS OPERATIONS

This section describes the requirements and use of thedevice bus operations, which are initiated through theinternal command register. The command registeritself does not occupy any addressable memory loca-tion. The register is composed of latches that store thecommands, along with the address and data informa-tion needed to execute the command. The contents of

Table 1.

the register serve as inputs to the internal statemachine. The state machine outputs dictate the func-tion of the device. Table 1 lists the device bus opera-tions, the inputs and control levels they require, and theresulting output. The following subsections describeeach of these operations in further detail.

Am29LV800B Device Bus Operations

DQ8–DQ15

Addresses(Note 1)

AINAINXXX

Sector Address, A6 = L, A1 = H,

A0 = LSector Address, A6 = H, A1 = H,

A0 = L

AIN

DQ0–DQ7DOUTDINHigh-ZHigh-ZHigh-ZDIN

BYTE#= VIHDOUTDINHigh-ZHigh-ZHigh-ZX

BYTE# = VIL

DQ8–DQ14 = High-Z,

DQ15 = A-1

High-ZHigh-ZHigh-ZX

Operation

ReadWriteStandbyOutput DisableReset

Sector Protect (Note 2)

CE#LLVCC ± 0.3 VLXL

OE#WE#RESET#LHXHXH

HLXHXL

HHVCC ± 0.3 VHLVID

Sector Unprotect (Note 2)Temporary Sector Unprotect

LX

HX

LX

VIDVID

DINDIN

XDIN

XHigh-Z

Legend:L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, AIN = Address In, DIN = Data In, DOUT = Data OutNotes:1.Addresses are A18:A0 in word mode (BYTE# = VIH), A18:A-1 in byte mode (BYTE# = VIL).2.The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector Protection/Unprotection” section.Word/Byte Configuration

The BYTE# pin controls whether the device data I/Opins DQ15–DQ0 operate in the byte or word configura-tion. If the BYTE# pin is set at logic ‘1’, the device is inword configuration, DQ15–DQ0 are active and con-trolled by CE# and OE#.

If the BYTE# pin is set at logic ‘0’, the device is in byteconfiguration, and only data I/O pins DQ0–DQ7 are ac-tive and controlled by CE# and OE#. The data I/O pinsDQ8–DQ14 are tri-stated, and the DQ15 pin is used asan input for the LSB (A-1) address function.

The internal state machine is set for reading arraydata upon device power-up, or after a hardware reset.This ensures that no spurious alteration of the mem-ory content occurs during the power transition. Nocommand is necessary in this mode to obtain arraydata. Standard microprocessor read cycles that as-sert valid addresses on the device address inputs pro-duce valid data on the device data outputs. The deviceremains enabled for read access until the commandregister contents are altered.

See “Reading Array Data” for more information. Referto the AC Read Operations table for timing specifica-tions and to Figure 13 for the timing diagram. ICC1 inthe DC Characteristics table represents the active cur-rent specification for reading array data.

Requirements for Reading Array Data

To read array data from the outputs, the system mustdrive the CE# and OE# pins to VIL. CE# is the powercontrol and selects the device. OE# is the output con-trol and gates array data to the output pins. WE# shouldremain at VIH. The BYTE# pin determines whether thedevice outputs array data in words or bytes.

Writing Commands/Command Sequences

To write a command or command sequence (which in-cludes programming data to the device and erasing

Am29LV800B9

sectors of memory), the system must drive WE# andCE# to VIL, and OE# to VIH.

For program operations, the BYTE# pin determineswhether the device accepts program data in bytes orwords. Refer to “Word/Byte Configuration” for moreinformation.

The device features an Unlock Bypass mode to facili-tate faster programming. Once the device enters the Un-lock Bypass mode, only two write cycles are required toprogram a word or byte, instead of four. The “Word/ByteProgram Command Sequence” section has details onprogramming data to the device using both standard andUnlock Bypass command sequences.

An erase operation can erase one sector, multiple sec-tors, or the entire device. Tables 2 and 3 indicate theaddress space that each sector occupies. A “sector ad-dress” consists of the address bits required to uniquelyselect a sector. The “Command Definitions” sectionhas details on erasing a sector or the entire chip, orsuspending/resuming the erase operation.

After the system writes the autoselect command se-quence, the device enters the autoselect mode. Thesystem can then read autoselect codes from the inter-nal register (which is separate from the memory array)on DQ7–DQ0. Standard read cycle timings apply in thismode. Refer to the “Autoselect Mode” and “AutoselectCommand Sequence” sections for more information.ICC2 in the DC Characteristics table represents the ac-tive current specification for the write mode. The “ACCharacteristics” section contains timing specificationtables and timing diagrams for write operations.

device is in either of these standby modes, before it isready to read data.

If the device is deselected during erasure or program-ming, the device draws active current until theoperation is completed.

In the DC Characteristics table, ICC3 and ICC4 repre-sents the standby current specification.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash deviceenergy consumption. The device automatically enablesthis mode when addresses remain stable for tACC + 30ns. The automatic sleep mode is independent of theCE#, WE#, and OE# control signals. Standard addressaccess timings provide new data when addresses arechanged. While in sleep mode, output data is latchedand always available to the system. ICC4 in the DCCharacteristics table represents the automatic sleepmode current specification.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of reset-ting the device to reading array data. When the RE-SET# pin is driven low for at least a period of tRP, thedevice immediately terminates any operation inprogress, tristates all output pins, and ignores allread/write commands for the duration of the RESET#pulse. The device also resets the internal state ma-chine to reading array data. The operation that was in-terrupted should be reinitiated once the device is readyto accept another command sequence, to ensure dataintegrity.

Current is reduced for the duration of the RESET#pulse. When RESET# is held at VSS±0.3 V, the devicedraws CMOS standby current (ICC4). If RESET# is heldat VIL but not within VSS±0.3 V, the standby current willbe greater.

The RESET# pin may be tied to the system reset cir-cuitry. A system reset would thus also reset the Flashmemory, enabling the system to read the boot-up firm-ware from the Flash memory.

If RESET# is asserted during a program or erase op-eration, the RY/BY# pin remains a “0” (busy) until theinternal reset operation is complete, which requires atime of tREADY (during Embedded Algorithms). Thesystem can thus monitor RY/BY# to determinewhether the reset operation is complete. If RESET# isasserted when a program or erase operation is not ex-ecuting (RY/BY# pin is “1”), the reset operation iscompleted within a time of tREADY (not during Embed-ded Algorithms). The system can read data tRH afterthe RESET# pin returns to VIH.

Refer to the AC Characteristics tables for RESET# pa-rameters and to Figure 14 for the timing diagram.

Program and Erase Operation Status

During an erase or program operation, the system maycheck the status of the operation by reading the statusbits on DQ7–DQ0. Standard read cycle timings and ICCread specifications apply. Refer to “Write OperationStatus” for more information, and to “AC Characteris-tics” for timing diagrams.

Standby Mode

When the system is not reading or writing to the device,it can place the device in the standby mode. In thismode, current consumption is greatly reduced, and theoutputs are placed in the high impedance state, inde-pendent of the OE# input.

The device enters the CMOS standby mode when theCE# and RESET# pins are both held at VCC ± 0.3 V.(Note that this is a more restricted voltage range thanVIH.) If CE# and RESET# are held at VIH, but not withinVCC ± 0.3 V, the device will be in the standby mode, butthe standby current will be greater. The device requiresstandard access time (tCE) for read access when the

10Am29LV800B

Output Disable Mode

When the OE# input is at VIH, output from the device isdisabled. The output pins are placed in the high imped-ance state.

Table 2.Am29LV800BT Top Boot Block SectorAddresses

Sector Size(Kbytes/Kwords)64/3264/3264/3264/3264/3264/3264/3264/3264/3264/3264/3264/3264/3264/3264/3232/168/48/416/8

Address Range (in hexadecimal)(x8)

Address Range00000h–0FFFFh10000h–1FFFFh20000h–2FFFFh30000h–3FFFFh40000h–4FFFFh50000h–5FFFFh60000h–6FFFFh70000h–7FFFFh80000h–8FFFFh90000h–9FFFFhA0000h–AFFFFhB0000h–BFFFFhC0000h–CFFFFhD0000h–DFFFFhE0000h–EFFFFhF0000h–F7FFFhF8000h–F9FFFhFA000h–FBFFFhFC000h–FFFFFh

(x16)

Address Range00000h–07FFFh08000h–0FFFFh10000h–17FFFh18000h–1FFFFh20000h–27FFFh28000h–2FFFFh30000h–37FFFh38000h–3FFFFh40000h–47FFFh48000h–4FFFFh50000h–57FFFh58000h–5FFFFh60000h–67FFFh68000h–6FFFFh70000h–77FFFh78000h–7BFFFh7C000h–7CFFFh7D000h–7DFFFh7E000h–7FFFFh

SectorSA0SA1SA2SA3SA4SA5SA6SA7SA8SA9SA10SA11SA12SA13SA14SA15SA16SA17SA18

A180000000011111111111

A170000111100001111111

A160011001100110011111

A150101010101010101111

A14XXXXXXXXXXXXXXX0111

A13XXXXXXXXXXXXXXXX001

A12XXXXXXXXXXXXXXXX01X

Am29LV800B11

Table 3.

Am29LV800BB Bottom Boot Block SectorAddresses

Sector Size(Kbytes/Kwords)

16/88/48/432/1664/3264/3264/3264/3264/3264/3264/3264/3264/3264/3264/3264/3264/3264/3264/32

Address Range (in hexadecimal)(x8)

Address Range00000h–03FFFh04000h–05FFFh06000h–07FFFh08000h–0FFFFh10000h–1FFFFh20000h–2FFFFh30000h–3FFFFh40000h–4FFFFh50000h–5FFFFh60000h–6FFFFh70000h–7FFFFh80000h–8FFFFh90000h–9FFFFhA0000h–AFFFFhB0000h–BFFFFhC0000h–CFFFFhD0000h–DFFFFhE0000h–EFFFFhF0000h–FFFFFh

(x16)

Address Range00000h–01FFFh02000h–02FFFh03000h–03FFFh04000h–07FFFh08000h–0FFFFh10000h–17FFFh18000h–1FFFFh20000h–27FFFh28000h–2FFFFh30000h–37FFFh38000h–3FFFFh40000h–47FFFh48000h–4FFFFh50000h–57FFFh58000h–5FFFFh60000h–67FFFh68000h–6FFFFh70000h–77FFFh78000h–7FFFFh

SectorSA0SA1SA2SA3SA4SA5SA6SA7SA8SA9SA10SA11SA12SA13SA14SA15SA16SA17SA18

A180000000000011111111

A170000000111100001111

A160000011001100110011

A150000101010101010101

A140001XXXXXXXXXXXXXXX

A13011XXXXXXXXXXXXXXXX

A12X01XXXXXXXXXXXXXXXX

Note for Tables 2 and 3: Address range is A18:A-1 in byte mode and A18:A0 in word mode. See “Word/Byte Configuration” section.Autoselect Mode

The autoselect mode provides manufacturer and de-vice identification, and sector protection verification,through identifier codes output on DQ7–DQ0. Thismode is primarily intended for programming equipmentto automatically match a device to be programmed withits corresponding programming algorithm. However,the autoselect codes can also be accessed in-systemthrough the command register.

When using programming equipment, the autoselectmode requires VID (11.5 V to 12.5 V) on address pin A9.Address pins A6, A1, and A0 must be as shown in Table4. In addition, when verifying sector protection, the sec-tor address must appear on the appropriate highestorder address bits (see Tables 2 and 3). Table 4 showsthe remaining address bits that are don’t care. When allnecessary bits have been set as required, the program-ming equipment may then read the corresponding iden-tifier code on DQ7–DQ0.

To access the autoselect codes in-system, the hostsystem can issue the autoselect command via thecommand register, as shown in Table 5. This methoddoes not require VID. See “Command Definitions” fordetails on using the autoselect mode.

12Am29LV800B

Table 4.Am29LV800B Autoselect Codes (HighVoltageMethod)

A18A11to to

WE#A12A10HHHHH

X

X

VID

X

L

X

L

H

X

X

VID

X

L

X

L

H

X

X

A8toA7X

A5toA2X

DQ8toDQ15X22hX22hXX

DQ7toDQ001hDAhDAh5Bh5Bh01h (protected)00h (unprotected)

DescriptionModeCE#LLLLL

OE#LLLLL

A9VID

A6L

A1L

A0L

Manufacturer ID: AMDDevice ID: Am29LV800B(Top Boot Block)Device ID: Am29LV800B

(Bottom Boot Block)

WordByteWordByte

Sector Protection VerificationLLHSAX

VID

XLXHL

X

L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.Sector Protection/Unprotection

The hardware sector protection feature disables bothprogram and erase operations in any sector. The hard-ware sector unprotection feature re-enables both pro-gram and erase operations in previously protectedsectors.

The device is shipped with all sectors unprotected.AMD offers the option of programming and protectingsectors at its factory prior to shipping the devicethrough AMD’s ExpressFlash™ Service. Contact anAMD representative for details.

It is possible to determine whether a sector is protectedor unprotected. See “Autoselect Mode” for details.Sector Protection/unprotection can be implemented viatwo methods.

The primary method requires VID on the RESET# pinonly, and can be implemented either in-system or viaprogramming equipment. Figure 2 shows the algo-rithms and Figure 23 shows the timing diagram. Thismethod uses standard microprocessor bus cycle tim-ing. For sector unprotect, all unprotected sectors mustfirst be protected prior to the first sector unprotect writecycle.

The alternate method intended only for programmingequipment requires VID on address pin A9 and OE#.This method is compatible with programmer routineswritten for earlier 3.0 volt-only AMD flash devices. Pub-lication number 20536 contains further details; contactan AMD representative to request a copy.

Sector Unprotect mode is activated by setting the RE-SET# pin to VID. During this mode, formerly protectedsectors can be programmed or erased by selecting thesector addresses. Once VID is removed from the RE-SET# pin, all the previously protected sectors areprotectedagain. Figure 1 shows the algorithm, andFigure 22 shows the timing diagrams, for this feature.

START

RESET# = VID

(Note 1)Perform Erase orProgram Operations

RESET# = VIH

Temporary SectorUnprotect Completed

(Note 2)

Notes:1.All protected sectors unprotected.2.All previously protected sectors are protected once again.Temporary Sector Unprotect

This feature allows temporary unprotection of previ-ously protected sectors to change data in-system. The

Figure 1.Temporary Sector Unprotect Operation

Am29LV800B13

STARTPLSCNT = 1RESET# = VIDWait 1 µsProtect all sectors:The indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect addressSTARTPLSCNT = 1RESET# = VIDWait 1 µsTemporary SectorUnprotect ModeNoFirst Write Cycle = 60h?YesSet up sectoraddressSector Protect:Write 60h to sectoraddress withA6 = 0, A1 = 1, A0 = 0Wait 150 µsVerify Sector Protect: Write 40h to sector addresswith A6 = 0, A1 = 1, A0 = 0Read from sector addresswith A6 = 0, A1 = 1, A0 = 0NoNoFirst Write Cycle = 60h?YesAll sectorsprotected?YesSet up first sectoraddressSector Unprotect:Write 60h to sectoraddress withA6 = 1, A1 = 1, A0 = 0Temporary SectorUnprotect ModeIncrementPLSCNTResetPLSCNT = 1Wait 15 msVerify Sector Unprotect: Write 40h to sector address with A6 = 1, A1 = 1, A0 = 0Read from sector addresswith A6 = 1, A1 = 1, A0 = 0Set upnext sectoraddressNoNoPLSCNT= 25?YesData = 01h?YesYesDevice failedProtect anothersector?NoRemove VID from RESET#Write reset commandIncrementPLSCNTNoNoPLSCNT= 1000?YesData = 00h?YesDevice failedLast sectorverified?YesNoSector ProtectAlgorithmSector ProtectcompleteSector UnprotectAlgorithmRemove VID from RESET#Write reset commandSector UnprotectcompleteFigure 2.In-System Sector Protect/

Sector Unprotect Algorithms

14Am29LV800B

Hardware Data Protection

The command sequence requirement of unlock cyclesfor programming or erasing provides data protectionagainst inadvertent writes (refer to Table 5 for com-mand definitions). In addition, the following hardwaredata protection measures prevent accidental erasureor programming, which might otherwise be caused byspurious system level signals during VCC power-up andpower-down transitions, or from system noise.Low VCC Write Inhibit

When VCC is less than VLKO, the device does not ac-cept any write cycles. This protects data during VCCpower-up and power-down. The command register andall internal program/erase circuits are disabled, and thedevice resets. Subsequent writes are ignored until VCCis greater than VLKO. The system must provide the

proper signals to the control pins to prevent uninten-tional writes when VCC is greater than VLKO.Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE# orWE# do not initiate a write cycle.Logical Inhibit

Write cycles are inhibited by holding any one of OE# =VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,CE# and WE# must be a logical zero while OE# is alogical one.

Power-Up Write Inhibit

If WE# = CE# = VIL and OE# = VIH during power up, thedevice does not accept commands on the rising edgeof WE#. The internal state machine is automaticallyreset to reading array data on power-up.

COMMAND DEFINITIONS

Writing specific address and data commands or se-quences into the command register initiates device op-erations. Table 5 defines the valid register commandsequences. Writing incorrect address and data val-ues or writing them in the improper sequence resetsthe device to reading array data.

All addresses are latched on the falling edge of WE# orCE#, whichever happens later. All data is latched onthe rising edge of WE# or CE#, whichever happensfirst. Refer to the appropriate timing diagrams in the“AC Characteristics” section.

The Read Operations table provides the read parame-ters, and Figure 13 shows the timing diagram.

Reset Command

Writing the reset command to the device resets the de-vice to reading array data. Address bits are don’t carefor this command.

The reset command may be written between the se-quence cycles in an erase command sequence beforeerasing begins. This resets the device to reading arraydata. Once erasure begins, however, the device ig-nores reset commands until the operation is complete.The reset command may be written between the se-quence cycles in a program command sequence be-fore programming begins. This resets the device toreading array data (also applies to programming inErase Suspend mode). Once programming begins,however, the device ignores reset commands until theoperation is complete.

The reset command may be written between the se-quence cycles in an autoselect command sequence.Once in the autoselect mode, the reset command mustbe written to return to reading array data (also appliesto autoselect during Erase Suspend).

If DQ5 goes high during a program or erase operation,writing the reset command returns the device to read-ing array data (also applies during Erase Suspend).

Reading Array Data

The device is automatically set to reading array dataafter device power-up. No commands are required toretrieve data. The device is also ready to read arraydata after completing an Embedded Program or Em-bedded Erase algorithm.

After the device accepts an Erase Suspend com-mand, the device enters the Erase Suspend mode.The system can read array data using the standardread timings, except that if it reads at an addresswithin erase-suspended sectors, the device outputsstatus data. After completing a programming opera-tion in the Erase Suspend mode, the system mayonce again read array data with the same exception.See “Erase Suspend/Erase Resume Commands” formore information on this mode.

The system must issue the reset command to re-en-able the device for reading array data if DQ5 goes high,or while in the autoselect mode. See the “Reset Com-mand” section, next.

See also “Requirements for Reading Array Data” in the“Device Bus Operations” section for more information.

Autoselect Command Sequence

The autoselect command sequence allows the hostsystem to access the manufacturer and devices codes,and determine whether or not a sector is protected.Table 5 shows the address and data requirements. Thismethod is an alternative to that shown in Table 4, which

Am29LV800B15

is intended for PROM programmers and requires VIDon address bit A9.

The autoselect command sequence is initiated by writ-ing two unlock cycles, followed by the autoselect com-mand. The device then enters the autoselect mode,and the system may read at any address any numberof times, without initiating another command sequence. A read cycle at address XX00h retrieves the manufac-turer code. A read cycle at address XX01h in wordmode (or 02h in byte mode) returns the device code. Aread cycle containing a sector address (SA) and theaddress 02h in word mode (or 04h in byte mode) re-turns 01h if that sector is protected, or 00h if it is unpro-tected. Refer to Tables 2 and 3 for valid sectoraddresses.

The system must write the reset command to exit theautoselect mode and return to reading array data.

should be reinitiated once the device has reset to read-ing array data, to ensure data integrity.

Programming is allowed in any sequence and acrosssector boundaries. A bit cannot be programmedfrom a “0” back to a “1”. Attempting to do so may haltthe operation and set DQ5 to “1”, or cause the Data#Polling algorithm to indicate the operation was suc-cessful. However, a succeeding read will show that thedata is still “0”. Only erase operations can convert a “0”to a “1”.

Unlock Bypass Command Sequence

The unlock bypass feature allows the system to pro-gram bytes or words to the device faster than using thestandard program command sequence. The unlock by-pass command sequence is initiated by first writing twounlock cycles. This is followed by a third write cyclecontaining the unlock bypass command, 20h. The de-vice then enters the unlock bypass mode. A two-cycleunlock bypass program command sequence is all thatis required to program in this mode. The first cycle inthis sequence contains the unlock bypass programcommand, A0h; the second cycle contains the programaddress and data. Additional data is programmed inthe same manner. This mode dispenses with the initialtwo unlock cycles required in the standard programcommand sequence, resulting in faster total program-ming time. Table 5 shows the requirements for the com-mand sequence.

During the unlock bypass mode, only the Unlock By-pass Program and Unlock Bypass Reset commandsare valid. To exit the unlock bypass mode, the systemmust issue the two-cycle unlock bypass reset com-mand sequence. The first cycle must contain the data90h; the second cycle the data 00h. Addresses aredon’t care for both cycles. The device then returns toreading array data.

Figure 3 illustrates the algorithm for the program oper-ation. See the Erase/Program Operations table in “ACCharacteristics” for parameters, and to Figure 17 fortiming diagrams.

Word/Byte Program Command Sequence

The system may program the device by word or byte,depending on the state of the BYTE# pin. Program-ming is a four-bus-cycle operation. The program com-mand sequence is initiated by writing two unlock writecycles, followed by the program set-up command. Theprogram address and data are written next, which inturn initiate the Embedded Program algorithm. Thesystem is not required to provide further controls or tim-ings. The device automatically provides internally gen-erated program pulses and verifies the programmedcell margin. Table 5 shows the address and data re-quirements for the byte program command sequence.When the Embedded Program algorithm is complete,the device then returns to reading array data and ad-dresses are no longer latched. The system can deter-mine the status of the program operation by using DQ7,DQ6, or RY/BY#. See “Write Operation Status” for in-formation on these status bits.

Any commands written to the device during the Em-bedded Program Algorithm are ignored. Note that ahardware reset immediately terminates the program-ming operation. The program command sequence

16Am29LV800B

STARTThe system can determine the status of the erase op-eration by using DQ7, DQ6, DQ2, or RY/BY#. See“Write Operation Status” for information on these sta-tus bits. When the Embedded Erase algorithm is com-plete, the device returns to reading array data andaddresses are no longer latched.

Figure 4 illustrates the algorithm for the erase opera-tion. See the Erase/Program Operations tables in “ACCharacteristics” for parameters, and to Figure 18 fortiming diagrams.

Write ProgramCommand SequenceEmbeddedProgramalgorithm in progressData Poll from SystemSector Erase Command Sequence

Sector erase is a six bus cycle operation. The sectorerase command sequence is initiated by writing two un-lock cycles, followed by a set-up command. Two addi-tional unlock write cycles are then followed by theaddress of the sector to be erased, and the sectorerase command. Table 5 shows the address and datarequirements for the sector erase command sequence.The device does not require the system to preprogramthe memory prior to erase. The Embedded Erase algo-rithm automatically programs and verifies the sector foran all zero data pattern prior to electrical erase. Thesystem is not required to provide any controls or tim-ings during these operations.

After the command sequence is written, a sector erasetime-out of 50 µs begins. During the time-out period,additional sector addresses and sector erase com-mands may be written. Loading the sector erase buffermay be done in any sequence, and the number of sec-tors may be from one sector to all sectors. The time be-tween these additional cycles must be less than 50 µs,otherwise the last address and command might not beaccepted, and erasure may begin. It is recommendedthat processor interrupts be disabled during this time toensure all commands are accepted. The interrupts canbe re-enabled after the last Sector Erase command iswritten. If the time between additional sector erasecommands can be assumed to be less than 50 µs, thesystem need not monitor DQ3. Any command otherthan Sector Erase or Erase Suspend during thetime-out period resets the device to reading arraydata. The system must rewrite the command sequenceand any additional sector addresses and commands.The system can monitor DQ3 to determine if the sectorerase timer has timed out. (See the “DQ3: Sector EraseTimer” section.) The time-out begins from the risingedge of the final WE# pulse in the command sequence.Once the sector erase operation has begun, only theErase Suspend command is valid. All other commandsare ignored. Note that a hardware reset during thesector erase operation immediately terminates theoperation. The Sector Erase command sequenceshould be reinitiated once the device has returned toreading array data, to ensure data integrity.

Verify Data?NoYesNoIncrement AddressLast Address?YesProgramming CompletedNote: See Table 5 for program command sequence.Figure 3.Program Operation

Chip Erase Command Sequence

Chip erase is a six bus cycle operation. The chip erasecommand sequence is initiated by writing two unlockcycles, followed by a set-up command. Two additionalunlock write cycles are then followed by the chip erasecommand, which in turn invokes the Embedded Erasealgorithm. The device does not require the system topreprogram prior to erase. The Embedded Erase algo-rithm automatically preprograms and verifies the entirememory for an all zero data pattern prior to electricalerase. The system is not required to provide any con-trols or timings during these operations. Table 5 showsthe address and data requirements for the chip erasecommand sequence.

Any commands written to the chip during the Embed-ded Erase algorithm are ignored. Note that a hardwarereset during the chip erase operation immediately ter-minates the operation. The Chip Erase command se-quence should be reinitiated once the device hasreturned to reading array data, to ensure data integrity.

Am29LV800B17

When the Embedded Erase algorithm is complete, thedevice returns to reading array data and addresses areno longer latched. The system can determine the sta-tus of the erase operation by using DQ7, DQ6, DQ2, orRY/BY#. Refer to “Write Operation Status” for informa-tion on these status bits.

Figure 4 illustrates the algorithm for the erase opera-tion. Refer to the Erase/Program Operations tables inthe “AC Characteristics” section for parameters, and toFigure 18 for timing diagrams.

ation. See “Write Operation Status” for more informa-tion.

The system may also write the autoselect commandsequence when the device is in the Erase Suspendmode. The device allows reading autoselect codeseven at addresses within erasing sectors, since thecodes are not stored in the memory array. When thedevice exits the autoselect mode, the device reverts tothe Erase Suspend mode, and is ready for anothervalid operation. See “Autoselect Command Sequence”for more information.

The system must write the Erase Resume command(address bits are “don’t care”) to exit the erase suspendmode and continue the sector erase operation. Furtherwrites of the Resume command are ignored. AnotherErase Suspend command can be written after the de-vice has resumed erasing.

Erase Suspend/Erase Resume Commands

The Erase Suspend command allows the system to in-terrupt a sector erase operation and then read datafrom, or program data to, any sector not selected forerasure. This command is valid only during the sectorerase operation, including the 50 µs time-out periodduring the sector erase command sequence. TheErase Suspend command is ignored if written duringthe chip erase operation or Embedded Program algo-rithm. Writing the Erase Suspend command during theSector Erase time-out immediately terminates thetime-out period and suspends the erase operation. Ad-dresses are “don’t-cares” when writing the Erase Sus-pend command.

When the Erase Suspend command is written during asector erase operation, the device requires a maximumof 20 µs to suspend the erase operation. However,when the Erase Suspend command is written duringthe sector erase time-out, the device immediately ter-minates the time-out period and suspends the eraseoperation.

After the erase operation has been suspended, thesystem can read array data from or program data toany sector not selected for erasure. (The device “erasesuspends” all sectors selected for erasure.) Normalread and write timings and command definitions apply.Reading at any address within erase-suspended sec-tors produces status data on DQ7–DQ0. The systemcan use DQ7, or DQ6 and DQ2 together, to determineif a sector is actively erasing or is erase-suspended.See “Write Operation Status” for information on thesestatus bits.

After an erase-suspended program operation is com-plete, the system can once again read array data withinnon-suspended sectors. The system can determinethe status of the program operation using the DQ7 orDQ6 status bits, just as in the standard program oper-

STARTWrite Erase Command SequenceData Poll from SystemNoEmbedded Erasealgorithmin progressData = FFh?YesErasure CompletedNotes:1.See Table 5 for erase command sequence.2.See “DQ3: Sector Erase Timer” for more information.Figure 4.Erase Operation

18Am29LV800B

Table 5.

CommandSequence(Note 1)

Read (Note 6)Reset (Note 7)

Manufacturer ID

WordByteWordByteWordByteWord

4

ByteWordByteWordByte

43226611

AAA555AAA555AAAXXXXXX555AAA555AAAXXXXXX

Am29LV800B Command Definitions

Bus Cycles (Notes 2-5)

Second Third Fourth Fifth Sixth Addr

Data

Addr

DataAddr

Data

AddrData

Addr

Data

RDF0AAAAAA

2AA5552AA5552AA5552AA

AA

555

AAAAA090AAAAB030

2AA5552AA555PAXXX2AA5552AA555

5555PD005555

555AAA555AAA

8080

555AAA555AAA

AAAA

2AA5552AA555

5555

555AAASA

1030

55

AAA555AAA555AAA

A020

555555

555AAA555AAA555AAA555

90909090

X00X01

X02

CyclesFirstAddrRAXXX555AAA555AAA555AAA555

Data

11444

0122DADA225B5BXX00XX010001PD

Autoselect (Note 8)Device ID,

Top Boot Block Device ID,

Bottom Boot BlockSector Protect Verify (Note 9)

X01

X02

(SA)X02(SA)X04PA

ProgramUnlock Bypass

Unlock Bypass Program (Note 10)Unlock Bypass Reset (Note 11)Chip EraseSector Erase

Erase Suspend (Note 12)Erase Resume (Note 13)

WordByteWordByte

Legend:X = Don’t careRA = Address of the memory location to be read. RD = Data read from location RA during read operation.PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse, whichever happens later.Notes:1.See Table 1 for description of bus operations.2.All values are in hexadecimal.3.Except when reading array or autoselect data, all bus cyclesare write operations.4.Data bits DQ15–DQ8 are don’t cares for unlock andcommand cycles.5.Address bits A18–A11 are don’t cares for unlock andcommand cycles, unless PA or SA required.6.No unlock or command cycles required when reading arraydata.7.The Reset command is required to return to reading arraydata when device is in the autoselect mode, or if DQ5 goeshigh (while the device is providing status data).8.The fourth cycle of the autoselect command sequence is aread cycle.PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first.SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A18–A12 uniquely select any sector.9.The data is 00h for an unprotected sector and 01h for aprotected sector. See “Autoselect Command Sequence” formore information.10.The Unlock Bypass command is required prior to the UnlockBypass Program command.11.The Unlock Bypass Reset command is required to return toreading array data when the device is in the unlock bypassmode.12.The system may read and program in non-erasing sectors, orenter the autoselect mode, when in the Erase Suspendmode. The Erase Suspend command is valid only during asector erase operation.13.The Erase Resume command is valid only during the Erase Suspend mode.Am29LV800B19

WRITE OPERATION STATUS

The device provides several bits to determine the sta-tus of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7,and RY/BY#. Table 6 and the following subsections de-scribe the functions of these bits. DQ7, RY/BY#, andDQ6 each offer a method for determining whether aprogram or erase operation is complete or in progress.These three bits are discussed first.

Table 6 shows the outputs for Data# Polling on DQ7.Figure 5 shows the Data# Polling algorithm.

STARTDQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host systemwhether an Embedded Algorithm is in progress or com-pleted, or whether the device is in Erase Suspend.Data# Polling is valid after the rising edge of the finalWE# pulse in the program or erase command sequence.During the Embedded Program algorithm, the deviceoutputs on DQ7 the complement of the datum pro-grammed to DQ7. This DQ7 status also applies to pro-gramming during Erase Suspend. When theEmbedded Program algorithm is complete, the deviceoutputs the datum programmed to DQ7. The systemmust provide the program address to read valid statusinformation on DQ7. If a program address falls within aprotected sector, Data# Polling on DQ7 is active for ap-proximately 1 µs, then the device returns to readingarray data.

During the Embedded Erase algorithm, Data# Pollingproduces a “0” on DQ7. When the Embedded Erase al-gorithm is complete, or if the device enters the EraseSuspend mode, Data# Polling produces a “1” on DQ7.This is analogous to the complement/true datum outputdescribed for the Embedded Program algorithm: theerase function changes all the bits in a sector to “1”;prior to this, the device outputs the “complement,” or“0.” The system must provide an address within any ofthe sectors selected for erasure to read valid status in-formation on DQ7.

After an erase command sequence is written, if all sec-tors selected for erasing are protected, Data# Pollingon DQ7 is active for approximately 100 µs, then the de-vice returns to reading array data. If not all selectedsectors are protected, the Embedded Erase algorithmerases the unprotected sectors, and ignores the se-lected sectors that are protected.

When the system detects DQ7 has changed from thecomplement to true data, it can read valid data at DQ7–DQ0 on the following read cycles. This is because DQ7may change asynchronously with DQ0–DQ6 whileOutput Enable (OE#) is asserted low. Figure 19, Data#Polling Timings (During EmbeddedAlgorithms), in the“AC Characteristics” section illustrates this.

Read DQ7–DQ0Addr = VADQ7 = Data?YesNoNoDQ5 = 1?YesRead DQ7–DQ0Addr = VADQ7 = Data?YesNoFAILPASSNotes:1.VA = Valid address for programming. During a sector erase operation, a valid address is an address within any sector selected for erasure. During chip erase, a valid address is any non-protected sector address.2.DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5.Figure 5.Data# Polling Algorithm

20Am29LV800B

RY/BY#: Ready/Busy#

The RY/BY# is a dedicated, open-drain output pin thatindicates whether an Embedded Algorithm is inprogress or complete. The RY/BY# status is valid afterthe rising edge of the final WE# pulse in the commandsequence. Since RY/BY# is an open-drain output, sev-eral RY/BY# pins can be tied together in parallel with apull-up resistor to VCC.

If the output is low (Busy), the device is actively erasingor programming. (This includes programming in theErase Suspend mode.) If the output is high (Ready),the device is ready to read array data (including duringthe Erase Suspend mode), or is in the standby mode.Table 6 shows the outputs for RY/BY#. Figures 13, 14,17 and 18 shows RY/BY# for read, reset, program, anderase operations, respectively.

Table 6 shows the outputs for Toggle Bit I on DQ6. Fig-ure 6 shows the toggle bit algorithm. Figure 20 in the“AC Characteristics” section shows the toggle bit timingdiagrams. Figure 21 shows the differences betweenDQ2 and DQ6 in graphical form. See also the subsec-tion on “DQ2: Toggle Bit II”.

DQ2: Toggle Bit II

The “Toggle Bit II” on DQ2, when used with DQ6, indi-cates whether a particular sector is actively erasing(that is, the Embedded Erase algorithm is in progress),or whether that sector is erase-suspended. Toggle BitII is valid after the rising edge of the final WE# pulse inthe command sequence.

DQ2 toggles when the system reads at addresseswithin those sectors that have been selected for era-sure. (The system may use either OE# or CE# to con-trol the read cycles.) But DQ2 cannot distinguishwhether the sector is actively erasing or is erase-sus-pended. DQ6, by comparison, indicates whether thedevice is actively erasing, or is in Erase Suspend, butcannot distinguish which sectors are selected for era-sure. Thus, both status bits are required for sector andmode information. Refer to Table 6 to compare outputsfor DQ2 and DQ6.

Figure 6 shows the toggle bit algorithm in flowchartform, and the section “DQ2: Toggle Bit II” explains thealgorithm. See also the “DQ6: Toggle Bit I” subsection.Figure 20 shows the toggle bit timing diagram. Figure21 shows the differences between DQ2 and DQ6 ingraphical form.

DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whether an EmbeddedProgram or Erase algorithm is in progress or complete,or whether the device has entered the Erase Suspendmode. Toggle Bit I may be read at any address, and isvalid after the rising edge of the final WE# pulse in thecommand sequence (prior to the program or erase op-eration), and during the sector erase time-out.During an Embedded Program or Erase algorithm op-eration, successive read cycles to any address causeDQ6 to toggle. (The system may use either OE# orCE# to control the read cycles.) When the operation iscomplete, DQ6 stops toggling.

After an erase command sequence is written, if all sec-tors selected for erasing are protected, DQ6 toggles forapproximately 100 µs, then returns to reading arraydata. If not all selected sectors are protected, the Em-bedded Erase algorithm erases the unprotected sec-tors, and ignores the selected sectors that areprotected.

The system can use DQ6 and DQ2 together to deter-mine whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (that is,the Embedded Erase algorithm is in progress), DQ6toggles. When the device enters the Erase Suspendmode, DQ6 stops toggling. However, the system mustalso use DQ2 to determine which sectors are erasingor erase-suspended. Alternatively, the system can useDQ7 (see the subsection on “DQ7: Data# Polling”).If a program address falls within a protected sector,DQ6 toggles for approximately 1 µs after the programcommand sequence is written, then returns to readingarray data.

DQ6 also toggles during the erase-suspend-programmode, and stops toggling once the Embedded Pro-gram algorithm is complete.

Reading Toggle Bits DQ6/DQ2

Refer to Figure 6 for the following discussion. Wheneverthe system initially begins reading toggle bit status, itmust read DQ7–DQ0 at least twice in a row to determinewhether a toggle bit is toggling. Typically, the systemwould note and store the value of the toggle bit after thefirst read. After the second read, the system would com-pare the new value of the toggle bit with the first. If thetoggle bit is not toggling, the device has completed theprogram or erase operation. The system can read arraydata on DQ7–DQ0 on the following read cycle.However, if after the initial two read cycles, the systemdetermines that the toggle bit is still toggling, the sys-tem also should note whether the value of DQ5 is high(see the section on DQ5). If it is, the system shouldthen determine again whether the toggle bit is toggling,since the toggle bit may have stopped toggling just asDQ5 went high. If the toggle bit is no longer toggling,the device has successfully completed the program orerase operation. If it is still toggling, the device did notcompleted the operation successfully, and the systemmust write the reset command to return to readingarray data.

Am29LV800B21

The remaining scenario is that the system initially de-termines that the toggle bit is toggling and DQ5 has notgone high. The system may continue to monitor thetoggle bit and DQ5 through successive read cycles, de-termining the status as described in the previous para-graph. Alternatively, it may choose to perform othersystem tasks. In this case, the system must start at thebeginning of the algorithm when it returns to determinethe status of the operation (top of Figure 6).

STARTRead DQ7–DQ0(Note 1)DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase time hasexceeded a specified internal pulse count limit. Underthese conditions DQ5 produces a “1.” This is a failurecondition that indicates the program or erase cycle wasnot successfully completed.

The DQ5 failure condition may appear if the systemtries to program a “1” to a location that is previously pro-grammed to “0.” Only an erase operation can changea “0” back to a “1.” Under this condition, the devicehalts the operation, and when the operation has ex-ceeded the timing limits, DQ5 produces a “1.”Under both these conditions, the system must issue thereset command to return the device to reading arraydata.

Read DQ7–DQ0Toggle Bit = Toggle?YesNoNoDQ5 = 1?YesRead DQ7–DQ0Twice(Notes1, 2)DQ3: Sector Erase Timer

After writing a sector erase command sequence, thesystem may read DQ3 to determine whether or not anerase operation has begun. (The sector erase timerdoes not apply to the chip erase command.) If additionalsectors are selected for erasure, the entire time-out alsoapplies after each additional sector erase command.When the time-out is complete, DQ3 switches from “0” to“1.” The system may ignore DQ3 if the system canguarantee that the time between additional sectorerase commands will always be less than 50 µs. Seealso the “Sector Erase Command Sequence” section.After the sector erase command sequence is written,the system should read the status on DQ7 (Data# Poll-ing) or DQ6 (Toggle Bit I) to ensure the device has ac-cepted the command sequence, and then read DQ3. IfDQ3 is “1”, the internally controlled erase cycle has be-gun; all further commands (other than Erase Suspend)are ignored until the erase operation is complete. IfDQ3 is “0”, the device will accept additional sectorerase commands. To ensure the command has beenaccepted, the system software should check the statusof DQ3 prior to and following each subsequent sectorerase command. If DQ3 is high on the second statuscheck, the last command might not have been ac-cepted. Table 6 shows the outputs for DQ3.

Toggle Bit = Toggle?YesProgram/EraseOperation Not Complete, Write Reset CommandNoProgram/EraseOperation CompleteNotes:1.Read toggle bit twice to determine whether or not it is toggling. See text.2.Recheck toggle bit because it may stop toggling as DQ5 changes to “1”. See text.Figure 6.Toggle Bit Algorithm

22Am29LV800B

Table 6.

Operation

Standard Embedded Program AlgorithmModeEmbedded Erase AlgorithmErase Suspend Mode

Reading within Erase Suspended SectorReading within Non-Erase Suspended SectorErase-Suspend-Program

Write Operation Status

DQ6ToggleToggleNo toggleDataToggle

DQ5(Note 1)

000Data0

DQ3N/A1N/ADataN/A

DQ2(Note 2)No toggleToggleToggleDataN/A

RY/BY#

00110

DQ7(Note 2)DQ7#01DataDQ7#

Notes:1.DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. See “DQ5: Exceeded Timing Limits” for more information.2.DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.Am29LV800B23

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°CAmbient Temperature

with Power Applied. . . . . . . . . . . . . . –65°C to +125°CVoltage with Respect to Ground

VCC (Note 1) . . . . . . . . . . . . . . . .–0.5 V to +4.0 VA9, OE#, and

RESET# (Note 2). . . . . . . . . . . .–0.5 V to +12.5 VAll other pins (Note 1) . . . . . –0.5 V to VCC+0.5 VOutput Short Circuit Current (Note 3) . . . . . . 200 mA

Notes:1.Minimum DC voltage on input or I/O pins is –0.5 V. Duringvoltage transitions, input or I/O pins may undershoot VSSto –2.0 V for periods of up to 20 ns. See Figure 7.Maximum DC voltage on input or I/O pins is VCC +0.5 V.During voltage transitions, input or I/O pins may overshootto VCC +2.0 V for periods up to 20 ns. See Figure 8.2.Minimum DC input voltage on pins A9, OE#, and RESET#is –0.5 V. During voltage transitions, A9, OE#, andRESET# may undershoot VSS to –2.0 V for periods of upto 20 ns. See Figure 7. Maximum DC input voltage on pinA9 is +12.5 V which may overshoot to 14.0 V for periodsup to 20 ns.3.No more than one output may be shorted to ground at atime. Duration of the short circuit should not be greaterthan one second.Stresses above those listed under “Absolute MaximumRatings” may cause permanent damage to the device. This isa stress rating only; functional operation of the device atthese or any other conditions above those indicated in theoperational sections of this data sheet is not implied.Exposure of the device to absolute maximum ratingconditions for extended periods may affect device reliability.OPERATING RANGES

Commercial (C) Devices

Ambient Temperature (TA) . . . . . . . . . . .0°C to +70°CIndustrial (I) Devices

Ambient Temperature (TA) . . . . . . . . .–40°C to +85°CExtended (E) Devices

Ambient Temperature (TA) . . . . . . . .–55°C to +125°CVCC Supply Voltages

VCC for regulated voltage range . . . . +3.0 V to +3.6 VVCC for full voltage range . . . . . . . . . +2.7 V to +3.6 V

Operating ranges define those limits between which thefunctionality of the device is guaranteed20 ns+0.8 V–0.5 V–2.0 V20 ns20 nsVCC+2.0 VVCC+0.5 V2.0 V

20 ns20 ns20 nsFigure 7.

Maximum Negative Overshoot

Waveform

Figure 8.

Maximum Positive Overshoot

Waveform

24Am29LV800B

DC CHARACTERISTICSCMOS Compatible

Parameter

ILIILITILO

Description

Input Load CurrentA9 Input Load CurrentOutput Leakage Current

Test Conditions

VIN = VSS to VCC, VCC = VCC max

VCC = VCC max; A9 = 12.5 VVOUT = VSS to VCC, VCC = VCC maxCE# = VIL, OE# = VIH,Byte Mode

CE# = VIL, OE# = VIH,Word Mode

CE# = VIL, OE# = VIHCE#, RESET# = VCC±0.3 VRESET# = VSS ± 0.3 VVIH = VCC ± 0.3 V; VIL = VSS ± 0.3 V

–0.50.7 x VCC

VCC = 3.3 V

11.5

5 MHz1 MHz5 MHz1 MHz

7272150.20.20.2

Min

Typ

Max±1.035±1.0124124305550.8VCC + 0.312.5

mAµAµAµAVVVVVmAUnitµAµAµA

ICC1

VCC Active Read Current (Notes 1, 2)

ICC2ICC3ICC4ICC5VILVIHVIDVOLVOH1VOH2VLKO

VCC Active Write Current (Notes 2, 3, 5)

VCC Standby Current (Note 2)VCC Reset Current (Note 2)Automatic Sleep Mode (Notes 2, 4)Input Low VoltageInput High Voltage

Voltage for Autoselect and Temporary Sector UnprotectOutput Low VoltageOutput High VoltageLow VCC Lock-Out Voltage (Note 4)

IOL = 4.0 mA, VCC = VCC min 0.45IOH = –2.0 mA, VCC = VCC min IOH = –100 µA, VCC = VCC min

0.85 VCCVCC–0.42.3

2.5

V

Notes:1.The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH. Typical VCC is 3.0 V.2.Maximum ICC specifications are tested with VCC = VCCmax.3.ICC active while Embedded Erase or Embedded Program is in progress.4.Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns.5.Not 100% tested.Am29LV800B25

DC CHARACTERISTICS (Continued)Zero Power Flash

20Supply Current in mA15

10

5

0

0

500

1000

1500

2000Time in ns

Note: Addresses are switching at 1 MHz2500300035004000

Figure 9.

ICC1 Current vs. Time (Showing Active and AutomaticSleepCurrents)

10

8Supply Current in mA3.6 V

6

2.7 V

4

2

01

2

3

Frequency in MHz

Note: T = 25 °C45

Figure 10.

Typical ICC1 vs. Frequency

26Am29LV800B

TEST CONDITIONS

3.3 V

2.7 kΩ

Table 7.

Test Condition

Test Specifications

-70

-90,-1201 TTL gate 30

50.0–3.0

100

pFnsVUnit

DeviceUnderTest

CL

6.2 kΩ

Output Load

Output Load Capacitance, CL(including jig capacitance) Input Rise and Fall TimesInput Pulse LevelsInput timing measurement reference levels

Output timing measurement reference levels

1.5 V1.5

V

Note: Diodes are IN3064 or equivalentFigure 11.Test Setup

KEY TO SWITCHING WAVEFORMS

WAVEFORM

INPUTS

Steady

Changing from H to LChanging from L to H

Don’t Care, Any Change Permitted

Does Not Apply

Changing, State Unknown

Center Line is High Impedance State (High Z)

OUTPUTS

3.0 V0.0 VInput1.5 VMeasurement Level1.5 VOutputFigure 12.Input Waveforms and

MeasurementLevels

Am29LV800B27

AC CHARACTERISTICSRead Operations

ParameterJEDECtAVAVtAVQVtELQVtGLQVtEHQZtGHQZ

StdtRCtACCtCEtOEtDFtDFtOEH

Description

Read Cycle Time (Note 1)Address to Output DelayChip Enable to Output DelayOutput Enable to Output DelayChip Enable to Output High Z (Note 1)Output Enable to Output High Z (Note 1)Output Enable Hold Time (Note 1)

ReadToggle and Data# Polling

CE# = VILOE# = VILOE# = VIL

Test Setup

MinMaxMaxMaxMaxMaxMinMinMin

Speed Options-70707070302525

-909090903530300100

-120120120120503030

Unitnsnsnsnsnsnsnsnsns

tAXQXtOH

Output Hold Time From Addresses, CE# or OE#, Whichever Occurs First (Note 1)

Notes:1.Not 100% tested.2.See Figure 11 and Table 7 for test specifications.tRCAddressesCE#tOEtOEHWE#HIGH ZtCEOutput ValidtOHHIGH ZtDFAddresses StabletACCOE#OutputsRESET#RY/BY#0 VFigure 13.Read Operations Timings

28Am29LV800B

AC CHARACTERISTICSHardware Reset (RESET#)

ParameterJEDEC

StdtREADYtREADYtRPtRHtRPDtRB

Description

RESET# Pin Low (During Embedded Algorithms) to Read or Write (See Note)RESET# Pin Low (NOT During Embedded Algorithms) to Read or Write (See Note)RESET# Pulse Width

RESET# High Time Before Read (See Note)RESET# Low to Standby ModeRY/BY# Recovery Time

Test Setup

MaxMaxMinMinMinMin

All Speed Options

2050050050200

Unitµsnsnsnsµsns

Note: Not 100% tested.RY/BY#CE#, OE#tRHRESET#tRPtReadyReset Timings NOT during Embedded AlgorithmsReset Timings during Embedded AlgorithmstReadyRY/BY#tRBCE#, OE#RESET#tRPFigure 14.RESET# Timings

Am29LV800B29

AC CHARACTERISTICS

Word/Byte Configuration (BYTE#)

Parameter

JEDEC

StdtELFL/tELFHtFLQZtFHQV

CE#

Description

CE# to BYTE# Switching Low or HighBYTE# Switching Low to Output HIGH ZBYTE# Switching High to Output Active

MaxMax Min

2570 -70

Speed Options

-9053090

30120-120

Unitnsnsns

OE#

BYTE#

tELFLBYTE#Switchingfrom wordto bytemode

DQ0–DQ14

Data Output(DQ0–DQ14)DQ15OutputtFLQZData Output(DQ0–DQ7)AddressInputDQ15/A-1

tELFHBYTE#

BYTE#Switchingfrom byteto wordmode

DQ0–DQ14

Data Output(DQ0–DQ7)AddressInputtFHQVData Output(DQ0–DQ14)DQ15OutputDQ15/A-1

Figure 15.BYTE# Timings for Read Operations

CE#

The falling edge of the last WE# signalWE#

BYTE#

tSET(tAS)tHOLD (tAH)Note: Refer to the Erase/Program Operations table for tAS and tAH specifications.Figure 16.BYTE# Timings for Write Operations

30Am29LV800B

AC CHARACTERISTICSErase/Program Operations

ParameterJEDECtAVAVtAVWLtWLAXtDVWHtWHDX

StdtWCtAStAHtDStDHtOES

tGHWLtELWLtWHEHtWLWHtWHWLtWHWH1tWHWH2

tGHWLtCStCHtWPtWPH

Description

Write Cycle Time (Note 1)Address Setup TimeAddress Hold TimeData Setup TimeData Hold Time

Output Enable Setup Time Read Recovery Time Before Write (OE# High to WE# Low)CE# Setup TimeCE# Hold TimeWrite Pulse WidthWrite Pulse Width High

ByteWord

MinMinMinMinMinMinMinMinMinMinMinTypTypTypMinMinMin

354535 -7070

Speed Options

-9090045450000035309110.750090

505050-120120

Unitnsnsnsnsnsnsnsnsnsnsnsµssecµsnsns

tWHWH1Programming Operation (Note 2)tWHWH2Sector Erase Operation (Note 2)tVCStRBtBUSY

VCC Setup Time (Note 1)Recovery Time from RY/BY#

Program/Erase Valid to RY/BY# Delay

Notes:1.Not 100% tested.2.See the “Erase and Programming Performance” section for more information.Am29LV800B31

AC CHARACTERISTICS

Program Command Sequence (last two cycles)tWCAddresses555htASPAtAHCE#OE#tWPWE#tCStDSDatatDHPDtBUSYRY/BY#VCCtVCSNotes:1.PA = program address, PD = program data, DOUT is the true data at the program address.2.Illustration shows device in word mode.Read Status Data (last two cycles)PAPAtCHtWHWH1tWPHA0hStatusDOUTtRBFigure 17.Program Operation Timings

32Am29LV800B

AC CHARACTERISTICS

Erase Command Sequence (last two cycles)tWCAddresses2AAhtASSA555h for chip eraseRead Status DataVAtAHVACE#tCHtWPWE#tCStDStDHData55h30h10 for Chip EraseInProgressCompleteOE#tWPHtWHWH2tBUSYRY/BY#tVCSVCCtRBNotes:1.SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).2.Illustration shows device in word mode.Figure 18.Chip/Sector Erase Operation Timings

Am29LV800B33

AC CHARACTERISTICS

tRCAddressesVAtACCCE#tCHOE#tOEHWE#tOHDQ7ComplementComplementTrueValid DataHigh ZVAVAtCEtOEtDFDQ0–DQ6tBUSYRY/BY#Status DataStatus DataTrueValid DataHigh ZNote: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array dataread cycle.Figure 19.Data# Polling Timings (During EmbeddedAlgorithms)

tRCAddressesVAtACCCE#tCHOE#tOEHWE#tOHDQ6/DQ2tBUSYRY/BY#High ZVAVAVAtCEtOEtDFValid Status(first read)Valid Status(second read)Valid Status(stops toggling)Valid DataNote: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status readcycle, and array data read cycle.Figure 20.Toggle Bit Timings (During EmbeddedAlgorithms)

34Am29LV800B

AC CHARACTERISTICS

EnterEmbeddedErasing

WE#

EraseSuspendEraseEnter EraseSuspend Program

EraseSuspendProgram

EraseResume

Erase Suspend

Read

Erase

EraseComplete

Erase SuspendRead

DQ6

DQ2

Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within anerase-suspended sector. Figure 21.DQ2 vs. DQ6

Temporary Sector Unprotect

ParameterJEDEC

StdtVIDRtRSP

Description

VID Rise and Fall Time (See Note)RESET# Setup Time for Temporary Sector Unprotect

MinMin

All Speed Options

5004

Unitnsµs

Note: Not 100% tested.12 VRESET#0 or 3 VtVIDRProgram or Erase Command SequencetVIDR0 or 3 VCE#WE#tRSPRY/BY# Figure 22.

Temporary Sector Unprotect TimingDiagram

Am29LV800B35

AC CHARACTERISTICS

VIDVIHRESET#SA, A6,A1, A0Valid*Sector Protect/UnprotectValid*Verify40hSector Protect: 150 µsSector Unprotect: 15 msValid*Data1 µsCE#60h60hStatusWE#OE#* For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.Figure 23.

Sector Protect/Unprotect TimingDiagram

36Am29LV800B

AC CHARACTERISTICSAlternate CE# Controlled Erase/Program Operations

ParameterJEDECtAVAVtAVELtELAXtDVEHtEHDX

StdtWCtAStAHtDStDHtOES

tGHELtWLELtEHWHtELEHtEHELtWHWH1tWHWH2

tGHELtWStWHtCPtCPHtWHWH1tWHWH2

Description

Write Cycle Time (Note 1)Address Setup TimeAddress Hold TimeData Setup TimeData Hold Time

Output Enable Setup TimeRead Recovery Time Before Write (OE# High to WE# Low)WE# Setup TimeWE# Hold TimeCE# Pulse WidthCE# Pulse Width HighProgramming Operation (Note 2)

Sector Erase Operation (Note 2)

ByteWord

MinMinMinMinMinMinMinMinMinMinMinTypTypTyp

354535-7070

Speed Options

-9090045450000035309110.7

505050-120120

Unitnsnsnsnsnsnsnsnsnsnsnsµssec

Notes:1.Not 100% tested.2.See the “Erase and Programming Performance” section for more information.Am29LV800B37

AC CHARACTERISTICS

555 for program2AA for erase PA for programSA for sector erase555 for chip erase Data# PollingPAAddressestWCtWHWE#tGHELOE#tCPCE#tWStCPHtDStDHDatatRHA0 for program55 for erase PD for program30 for sector erase10 for chip erase tAStAHtWHWH1 or 2tBUSYDQ7#DOUTRESET#RY/BY#Notes: 1.PA = program address, PD = program data, DQ7# = complement of the data written to the device, DOUT = data written to the device. 2.Figure indicates the last two bus cycles of command sequence.3.Word mode address used as an example.Figure 24.Alternate CE# Controlled Write OperationTimings

38Am29LV800B

ERASE AND PROGRAMMING PERFORMANCE

ParameterSector Erase TimeChip Erase Time Byte Programming TimeWord Programming TimeChip Programming Time(Note 3)

Byte ModeWord Mode

Typ (Note 1)

0.71491195.8

300360 2717Max (Note 2)

15

Unitssµsµsss

Excludes system level overhead (Note 5)

Comments

Excludes 00h programming prior to erasure

Notes:1.Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC, 1,000,000 cycles. Additionally, programming typicals assume checkerboard pattern.2.Under worst case conditions of 90°C, VCC = 2.7 V, 1,000,000 cycles.3.The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytesprogram faster than the maximum program times listed.4.In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.5.System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. SeeTable 5 for further information on command definitions.6.The device has a guaranteed minimum erase and program cycle endurance of 1,000,000 cycles.LATCHUP CHARACTERISTICS

Description

Input voltage with respect to VSS on all pins except I/O pins (including A9, OE#, and RESET#)

Input voltage with respect to VSS on all I/O pinsVCC Current

Min–1.0 V–1.0 V–100 mA

Max12.5 VVCC + 1.0 V+100 mA

Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time.TSOP AND SO PIN CAPACITANCE

Parameter Symbol

CINCOUTCIN2

Parameter DescriptionInput CapacitanceOutput CapacitanceControl Pin Capacitance

Test SetupVIN = 0VOUT = 0VIN = 0

Typ68.57.5

Max7.5129

UnitpFpFpF

Notes:1.Sampled, not 100% tested.2.Test conditions TA = 25°C, f = 1.0 MHz.DATA RETENTION

Parameter

Minimum Pattern Data Retention Time

Test Conditions

150°C125°C

Min1020

UnitYearsYears

Am29LV800B39

PHYSICAL DIMENSIONS*TS 048—48-Pin Standard TSOP

Dwg rev AA; 10/99* For reference only. BSC is an ANSI standard for Basic Space Centering.40Am29LV800B

PHYSICAL DIMENSIONSTSR048—48-Pin Reverse TSOP

Dwg rev AA; 10/99* For reference only. BSC is an ANSI standard for Basic Space Centering.Am29LV800B41

PHYSICAL DIMENSIONS

FBB 048—48-Ball Fine-Pitch Ball Grid Array (FBGA)6x9mm

Dwg rev AF; 10/9942Am29LV800B

PHYSICAL DIMENSIONS

SO 044—44-Pin Small Outline Package

Dwg rev AC; 10/9943Am29LV800B

REVISION SUMMARYRevision E (January 1998)

Distinctive Characteristics

Changed typical read and program/erase currentspecifications.

Device now has a guaranteed minimum endurance of1,000,000 write cycles.

In-System Sector Protect/Unprotect Algorithm Figure

Corrected A6 to 0, Changed wait specification to 150 µson sector protect and 15 ms on sector unprotect.DC Characteristics

Changed typical read and program/erase currentspecifications.AC Characteristics

Erase and Programming Performance

In Note 2, the worst case endurance is now 1 million cycles.

Revision F (January 1999)

Global

Changed references for process technology to “0.32µm.”

Replaced the 70R ns regulated voltage speed optionwith 70 ns full voltage speed option.Distinctive CharacteristicsAdded 20-year data retention bullet.Connection Diagrams

Reverse TSOP: Modified markings.

FBGA: Replaced Bump side (bottom) view with topview.

Ordering Information

Alternate CE# Controlled Erase/Program Operations:Changed tCP to 35 ns for 70R, 80, and 90 speed options.Erase and Programming Performance

Device now has a guaranteed minimum endurance of1,000,000 write cycles.Physical Dimensions

Corrected dimensions for package length and width inFBGA illustration (standalone data sheet version).

Valid Combinations for FBGA Packages: New Table.DC Characteristics—CMOS Compatible

ICC1, ICC2, ICC3, ICC4, ICC5: Added Note 2 “MaximumICC specifications are tested with VCC = VCCmax”.ICC3, ICC4: Deleted VCC = VCCmax.Physical Dimensions

Changed package drawing to FBB048.

Revision E+1 (March 1998)

In-System Sector Protect/Unprotect Algorithms Figure

In the sector protect algorithm, added a “ResetPLSCNT=1” box in the path from “Protect another sec-tor?” back to setting up the next sector address.DC Characteristics

Changed Note 1 to indicate that OE# is at VIH for thelisted current.AC Characteristics

Revision F+1 (February 1999)

Physical Dimensions

Corrected ball grid layout on FBB048 drawing. Added“048” to drawing title.

Revision F+2 (February 1999)

Distinctive Characteristics, Operating RangesCorrected to indicate that the VCC voltage range for alldevices is 2.7–3.6 V.

Erase/Program Operations; Alternate CE# ControlledErase/Program Operations: Corrected the notesreference for tWHWH1 and tWHWH2. These parametersare 100% tested. Corrected the note reference for tVCS.This parameter is not 100% tested.Temporary Sector Unprotect Table

Added note reference for tVIDR. This parameter is not100% tested.

Figure 23, Sector Protect/Unprotect Timing Diagram

A valid address is not required for the first write cycle;only the data 60h.

Revision F+3 (July 2, 1999)

Global

Added references to availability of device in KnownGood Die (KGD) form.

Revision F+4 (July 26, 1999)

Global

Added the 70R speed option, which is available in theextended temperature range. Ordering Information

Deleted the extended temperature range from theFBGA valid combinations.

Am29LV800B44

Revision G (November 10, 1999)

Ordering Information

Deleted commercial and industrial temperature rangesfrom the 70R speed option.

AC Characteristics—Figure 17. Program

Operations Timing and Figure 18. Chip/Sector Erase Operations

Deleted tGHWL and changed OE# waveform to start athigh.

Physical Dimensions

Replaced figures with more detailed illustrations.

Revision G+1 (July 7, 2000)

Ordering Information

Inserted dashes into ordering part numbers. Deletedburn-in option.

Revision G+2 (August 14, 2000)

Global

Deleted 70R and 80 ns speed options and burn-inoption.

TrademarksCopyright © 2000 Advanced Micro Devices, Inc. All rights reserved.

AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc.

Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

45Am29LV800B