Design of 60-GHz 90-nm CMOS Balanced Power Amplifier With Miniaturized Quadrature Hybrids

Miniaturized Quadrature Hybrids

Chien-Chih Lin, Chun-Han Yu, Hsin-Chih Kuo, and Huey-Ru Chuang

Institute of Computer and Communication Engineering, Department of Electrical Engineering,

National Cheng Kung University, Tainan, Taiwan, R.O.C.

Abstract — This paper presents a 60-GHz CMOS balanced power amplifier (PA) with miniaturized quadrature hybrids using 90-nm CMOS technology. To improve the output power and provide an area-efficient solution for the balanced PA design, a compact 3-dB quadrature hybrid constructed by a broadside-coupled scheme is employed as a low-insertion-loss power splitter/combiner. With a very short effective guided wavelength of 0.072 Ȝg, the simulated insertion loss and phase difference of the quadrature hybrids are better than 0.5 dB and 90° ± 0.2°, respectively. The designed PA reaches a power gain exceeding 13.2 dB and a saturation power of 10.7 dBm with a power-added efficiency (PAE) more than 9 % at 60 GHz. The power consumption of the PA is 109 mW at a 1.2 V supply voltage. The chip size is 0.68 mm2.

Fig. 1. Circuit schematic.

splitter/combiner design, has been studied on the monolithic microwave integrated circuit [7]. In this paper,

the design of a 60-GHz balanced PA in 90-nm CMOS with

I. INTRODUCTION the miniaturized 3-dB quadrature hybrids is demonstrated.

The PA cell contains a pair of three-stage common-source The millimeter-wave (MMW) wireless personal network

(WPAN) applications in V-band spectrum have been amplifiers which maximize the power gain. The high-progressively developed over the past decade due to its performance power splitter/combiner constructed by the high-speed data transmission and good communication low-insertion-loss and compact quadrature hybrids is security. Due to the increasing demands for the low-cost adopted to enhance the output power. In addition, a integration of the baseband and RF front-end circuits, the simplified output matching between the PA cell and the CMOS technology is an attractive solution to implement a quadrature hybrid is included. The designed PA has a highly-integrated MMW radio-on-chip (RoC). As there power gain more than 13.2 dB and a saturation power of are some major drawbacks such as the low 10.7 dBm with a PAE more than 9 % at 60 GHz. transconductance, low breakdown voltage and high silicon

II. CIRCUIT DEIGN

substrate loss in designing the CMOS power amplifier (PA), it is a challenge to provide the sufficient power gain, A. PA block power-added efficiency (PAE) and output power for the

Fig. 1 shows the entire circuit schematic of the proposed single-ended CMOS PA.

For the MMW CMOS PA design, the cascode topology PA. In order to maximize the output current/voltage swings is usually adopted to increase the power gain. However, a and power gain, the three-stage cascade configuration with higher supply voltage is needed and the output a 1.2 V supply voltage is adopted. To achieve a better current/voltage swing is limited. Therefore, the cascade linearity and an output power, the class-A biasing is chosen multi-stage common-source amplifier is a better choice for for the proposed PA (i.e. VGS = 0.85 V, VDS =1.2 V). Based a low-voltage operation [1]-[5]. In order to improve the on the maximum available gain and the load-pull analysis, output power of single-ended CMOS PAs, several power the characteristics of the transistors with different total combining methods such as the transformer coupling, widths are plotted in Fig. 2. The power transistor M3 is

selected to be 44 fingers with each finger width of 2 ȝm for direct combining, balanced topology, and metamaterial-the last stage to obtain a higher output power with a based zero phase shifter are exploited [1]-[5]. However, the

balanced PA is not a common architecture due to the large sufficient power gain. At the same time, the real part of the layout size and high insertion loss resulted from the use of optimum load Zopt can be apparently transformed to a

smaller value as the transistor size increases. Therefore, the input/output quadrature hybrids [6]. To tackle this problem,

a highly miniaturized and low-insertion-loss quadrature matching network between the output of the PA cell and

hybrid, by taking full advantage of a balanced power the quadrature hybrid input (as shown in Fig. 3)

Index Terms — 60 GHz, Balanced amplifier, CMOS,

Miniaturized quadrature hybrid, Power amplifier, V-band.

978-1-4799-2778-4/14/$31.00 © 2014 IEEE52PAWR 2014

1211GainPoutPAE4035302520S11S210-5S31S41Phase(S21)-Phase(S31)91

Pout (dBm) & Gain (dB)PAEGain1098Phase difference (deg.)S-parameters (dB) PAE (%)-10-15-20-25-30-35-40-40455055606570758010um90.5

15765Pout1050120Metal 1 (Ground)Metal 9 Metal 83um90

102030405060

708090100110Total Width of Transistor (Pm)

192um.5

Fig. 2. Characteristics of the transistors with different total widths.

Frequency (GHz)

Fig. 4. Simulated S-parameters and phase difference of the miniaturized 3-dB quadrature hybrid.

Total width = 40 umTotal width = 56 umTotal width = 72 umTotal width = 88 umFig. 3. Matching network between the PA cell and the 3-dB quadrature hybrid.

can be sufficiently simplified by a short stub circuit to reduce the extra matching loss and chip size. In addition, the finger numbers of the first (M1) and second (M2) stages, minimized to maintain a lower quiescent power and a higher PAE, are set to 16 and 28 fingers with each finger width of 2 ȝm, respectively.

where LM9 and LM8 are the self-inductances of the transformer lines, Cs,M9 and Cs,M8 are the parasitic capacitances between the transformer lines and the substrate, and Cn is the mutual capacitance between the transformer lines. In this design, k = 0.8, LM9 = LM8 = 91 pH, Cs,M9 = Cs,M8 = 3.81 fF and Cn = 15.23 fF, as used. By extracting the equivalent element value of the quadrature hybrid, the dimensions can then be designed and the effective guided wavelength is about 0.072 Ȝg, which is approximately 60 % size reduction compared to the broadside couplers in the balanced PA [6]. Fig. 4 shows the simulated insertion loss and the phase difference of the quadrature hybrid, which are better than 0.5 dB and 90° ± 0.2°, respectively.

III. MESUREMENT RESULTS

B. Miniaturized quadrature hybrid

The CMOS power splitter/combiner is constructed by using the miniaturized quadrature hybrid [7] and designed at the top (M9) and the eighth metal layer (M8). The structure can be analyzed as transformer lines and the coupling concept can be used to shorten the line length, which is also beneficial to the integrated circuit realization. The design parameters of the distributed elements can be expressed depended on the coupling coefficient k as:

LM9|LM8Cs,M9|Cs,M8

Z1 o

Ȧk

3k2󰀃2k2k2󰀃14󰀃2k2󰀄2k2k2󰀃1

(1)

Yok4󰀃2k2󰀄2k2k2󰀃1󰀃k2󰀄k4󰀄2k2k2󰀃1 (2) Ȧ󰀇1󰀄k󰀈3k2󰀃2k2k2󰀃1

kCn Cs,M9 (3)

1󰀃k

The designed 60-GHz CMOS balanced PA is fabricated in a 90-nm CMOS process. With a bias voltage (VDD) of 1.2 V, the power consumption of the proposed PA is 109 mW. Fig. 5 shows the measurement results of the input return loss (S11), output return loss (S22) and power gain (S21) from 50 to 67 GHz, respectively. The peak small signal gain of 19.8 dB is located at 57.3 GHz. The figure also shows the measured K-factor and reverse isolation of the PA. The circuit is unconditionally stable across the band with a reverse isolation better than 20 dB.

Fig. 6 shows the measured power gain, output power and PAE of the PA at 57.3 GHz and 60 GHz, respectively. At 57.3 GHz, the saturation power is about 10.7 dBm with the power gain of 19.8 dB. The PAE is 10 % and the output 1-dB compression point (OP1dB) is 7.5 dBm, respectively. At 60 GHz, the saturation power of the PA is close to 10.7 dBm with a power gain of 13.2 dB. The PAE is 9 % and the OP1dB is 9 dBm, respectively. Fig. 7 shows the output third-order intercept point (OIP3) of the PA is about 12 and 17.8 dBm at 57.3 and 60 GHz, respectively. The chip size is 0.68 mm2, including all contact-pads and dummy metals. Table I summarizes the measured performances and the comparison with the reported 60-GHz CMOS PAs. Overall, in terms of the power gain, output power, PAE, power consumption and die size, the proposed PA using

53

TABLE I PERFORMANCE COMPARISON OF V-BAND POWER AMPLIFIER [1] [2] [3] [4] [5] Reference This work2009 RFIC 2010 ISSCC2010 JSSC2012 APMC2013 MTT Technology 90-nm CMOS 65-nm CMOS65-nm CMOS65-nm CMOS65-nm CMOS 90-nm CMOS2-stage CS 3-stage CS2-stage CS 3-stage CS3-stage CS3-stage CSwith with Topology with 2 & 4-way with 4-way with 2-waywith 4-wayzero phase quadrature direct combining transformertransformertransformershifter hybrids RF frequency (GHz) 60 60 60 60 60 57.3 60 VDD (V) 1 0.91 1 1 1.2 1.2 1.2 Gain (dB) 8.2 4.2 18.919.216 2424.58.3 19.8 13.2 Saturation power (dBm) 11.6 14.2 16.817.711.5 1819 11 10.7 OP1dB (dBm) 10.1 12.1 13 15.15 14.815.49.7 7.5 9 Peak PAE (%) 11.5 5.8 10.811.115.2 13.212.87.1 10 9 Power consumption (mW) 81 145 41446050 500* 130* 109 2 Die size (mm) 1.03 1.2 0.83 0.7 0.740.6**0.39 0.68 *Estimated at the 1-dB compression point **Core area excluding DC bias pads K-factor252015S11S22S21S12109872520151050-5-10-15-20-25-30-35-40-45-50-20S-parameters (dB)1050-5-10-15-20-25-30505256586062666321Output Power (dBm)K-factorPout1 @ 60 GHzPout3 @ 60 GHzPout1 @ 57.3 GHzPout3 @ 57.3 GHz-15-10-505Frequency (GHz)

Input Power (dBm)Fig. 5. Measured S-parameters and K-factor. Also shown in the figure is a chip micrography.

Gain @ 60 GHzGain @ 57.3 GHz2015Pout @ 60 GHzPout @ 57.3 GHzPAE @ 60 GHzPAE @ 57.3 GHz1816Fig. 7. Measured OIP3 at 57.3 GHz and 60 GHz.

Pout (dBm) & Gain (dB)1050-5-10-15-20GainPout14121086

PAs. In addition, an simplified output matching between the PA cell and the quadrature hybrid is adopted to reduce the matching components, which can also reduce the matching loss and the chip size. The designed PA reaches a power gain exceeding 13.2 dB, a saturation power of 10.7 dBm, a PAE of 9 %, an OP1dB of 9 dBm and OIP3 of 17.8 dBm at 60 GHz with a supply voltage of 1.2 V. The chip size is 0.68 mm2.

PAE (%)PAE-15-10-50420REFERENCES

Input Power (dBm)

Fig. 6. Measured gain, output power, and PAE at 57.3 GHz and 60 GHz.

the miniaturized 3-dB quadrature hybrids exhibits a good performance compared with the reported works.

IV. CONCLUSION

A 60-GHz 90-nm CMOS balanced PA with miniaturized quadrature hybrids is designed and fabricated. The PA cell contains a pair of three-stage cascade amplifiers which maximize the power gain. The high-performance power splitter/combiner, constructed by the low-insertion-loss and compact quadrature hybrids, has provided the sufficient power splitting/combining and the area-efficient solution for the PA design, compared to the conventional balanced

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