V53C516165A资料

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V53C516165A5 VOLT 1M X 16 EDO PAGE MODECMOS DYNAMIC RAMHIGH PERFORMANCE

Max. RAS Access Time, (tRAC)

Max. Column Address Access Time, (tCAA)

Min. Extended Data Out Page Mode Cycle Time, (tPC)Min. Read/Write Cycle Time, (tRC)

50

50 ns25 ns20 ns84 ns

60

60 ns30 ns25 ns104 ns

Featuress1M x 16-bit organization

sEDO Page Mode for a sustained data rateof 50 MHz

sRAS access time: 50, 60 nssDual CAS InputssLow power dissipation

sRead-Modify-Write, RAS-Only Refresh, CAS-Before-RAS Refresh, Hidden Refresh, and Self Refresh.

sRefresh Interval: 4096 cycles/ ms

sAvailable in 42-pin 400 mil SOJ and 50/44-pin 400 mil TSOP-II Packages

sSingle +5.0 V ±10% Power SupplysLVTTL Interface

sRefresh Interval: 4096 cycles/256ms(L-versions)

DescriptionThe V53C516165A is a 1,048,576 x 16 bit high-performance CMOS dynamic random access mem-ory. The V53C516165A offers Page mode opera-tion with Extended Data Output. The V53C516165Ahas a symmetric address, 12-bit row and 8-bit col-umn.

All inputs are LVTTL compatible. EDO PageMode operation allows random access up to 256 x16 bits, within a page, with cycle times as short as20ns.

These features make the V53C516165A ideallysuited for a wide variety of high performance com-puter systems and peripheral applications.

Device Usage ChartOperatingTemperatureRange

0°C to 70 °C

Package OutlineK

•

Access Time (ns)50

•

PowerStd.

•

T

•

60

•

L

•

Temperature

Mark

Blank

V53C516165A Rev. 1.0 March 1998

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42-Pin Plastic SOJPIN CONFIGURATIONTop ViewVCCI/O1I/O2I/O3I/O4VCCI/O5I/O6I/O7I/O8NCNCWERASA11A10A0A1A2A3VCC1234567101112131415161718192021424140393837363534333231302928272625242322311816500-02V53C516165A50/44-Pin Plastic TSOP-IIPIN CONFIGURATIONTop ViewVCCI/O1I/O2I/O3I/O4VCCI/O5I/O6I/O7I/O8NC12345671011504948474443424140VSSI/O16I/O15I/O14I/O13VSSI/O12I/O11I/O10I/O9NCLCASUCASOEA9A8A7A6A5A4VSSVSSI/O16I/O15I/O14I/O13VSSI/O12I/O11I/O10I/O9NCNCNCWERASA11A10A0A1A2A3VCC15161718192021222324253635343332313029282726311816500-03NCLCASUCASOEA9A8A7A6A5A4VSSPin NamesA0–A11RASUCASLCASWEOEI/O1–I/O16VCCVSSNC

Row, Column Address InputsRow Address Strobe

Column Address Strobe/Upper Byte ControlColumn Address Strobe/Lower Byte ControlWrite EnableOutput EnableData Input, Output+5V Supply0V SupplyNo Connect

DescriptionSOJTSOP-II

Pkg.KT

Pin Count

4250/44

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Absolute Maximum Ratings*Operating temperature range..................0 to 70 °CStorage temperature range...............-55 to 150 °CSoldering temperature..................................260 °CSoldering time...................................................10 sInput/output voltage....-0.5 to min (VCC+0.5, 7.0) VPower supply voltage........................-1.0V to 7.0 VPower dissipation..........................................1.0 WData out current (short circuit)......................50 mA

*Note:Operation above Absolute Maximum Ratings can

adversely affect device reliability.

V53C516165ACapacitance*TA = 25°C, VCC =5 V ± 10%, VSS = 0 V, f = 1 MHz

SymbolCIN1CIN2COUT

Parameter Address InputRAS, UCAS, LCAS, WE, OEData Input/Output

Min.———

Max.577

UnitpFpFpF

*Note:Capacitance is sampled and not 100% tested.

Block DiagramOEWEUCASLCASRASRAS CLOCKGENERATORCAS CLOCKGENERATORWE CLOCKGENERATOROE CLOCKGENERATORVCCVSSDATA I/O BUSCOLUMN DECODERSY0–Y7I/O1I/O2I/O3I/O4I/O5I/O6I/O7REFRESHCOUNTER12A0A1SENSE AMPLIFIERS256 x 16I/OBUFFERI/O8I/O9I/O10I/O11ADDRESS BUFFERSAND PREDECODERSROWDECODERSX0– X114096I/O12A10A11•••MEMORYARRAY4096 x 256 x 16I/O13I/O14I/O15I/O16V53C516165A Rev. 1.0 March 1998

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DC and Operating Characteristics (1-2)

TA = 0°C to 70°C, VCC = 5.0 V ± 10%, VSS = 0 V, tT = 2ns, unless otherwise specified.

AccessTime

V53C516165AMin.

–10–10

5060

V53C516165ASymbol

ILIILOICC1

Parameter

Input Leakage Current (any input pin)

Output Leakage Current(for High-Z State)VCC Supply Current,Operating

VCC Supply Current,TTL StandbyVCC Supply Current,RAS-Only RefreshVCC Supply Current,EDO Page ModeOperation

VCC Supply Current,CMOS Standby

Average Self Refresh Current CBR cycle with tRAS > tRASS min., CAS held low, WE = VCC – 0.2V, Address and DIN = VCC – 0.2Vor 0.2V

VCC Supply Current,

during CAS-before-RAS RefreshInput Low VoltageInput High VoltageOutput Low VoltageOutput High Voltage

Typ.Max. Unit

1010100902

mAmAµAµAmA

Test Conditions

VSS ≤ VIN ≤ VCC + 0.3VVSS ≤ VOUT ≤ VCC + 0.3VRAS, CAS at VIHtRC = tRC (min.)

Notes

112, 3, 4

ICC2ICC3

RAS, CAS at VIHother inputs ≥ VSStRC = tRC (min.)

2, 4

50605060

1009070551.01.0250

ICC4

mAMinimum Cycle2, 3, 4

ICC5ICC6

mAmAµA

RAS ≥ VCC – 0.2 V,CAS ≥ VCC – 0.2 VL Version

1

ICC7

5060

–0.52

100900.8VCC+0.50.4

2.4

mA

tRC = tRC (min)

2, 4

VILVIHVOLVOH

VVVV

IOUT = 4.2 mAIOUT = –5 mA

1111

V53C516165A Rev. 1.0 March 1998

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AC Characteristics TA = 0°C to 70°C, VCC =5.0 V ±10%, VSS = 0V, tT = 2ns unless otherwise noted

JEDEC

SymbolSymbol

tRL1RH1tRL2RL2tRH2RL2tRL1CH1tCL1CH1tRL1CL1tWH2CL2tAVRL2tRL1AXtAVCL2tCL1AX

tRAStRCtRPtCSHtCAStRCDtRCStASRtRAHtASCtCAH

V53C516165A50

Parameter

RAS Pulse WidthRead or Write Cycle TimeRAS Precharge TimeCAS Hold TimeCAS Pulse WidthRAS to CAS DelayRead Command Setup TimeRow Address Setup TimeRow Address Hold TimeColumn Address Setup TimeColumn Address Hold TimeRAS Hold TimeCAS to RAS Precharge TimeRead Command Hold Time Referenced to CASRead Command Hold Time Referenced to RASOutput Hold after CAS LOWAccess Time from OEAccess Time from CASAccess Time from RASAccess Time from Column AddressCAS to Low-Z OutputOutput Buffer Turnoff DelayData to CAS Low DelayRAS to Column Address Delay TimeOutput Buffer Turnoff Delay from OEWrite Command to CAS Lead TimeWrite Command Setup TimeWrite Command Hold TimeWrite Pulse WidthData to OE DelayWrite Command to RAS Lead TimeData in Setup Time

000100130880130

251313

60Min.

601044050

10K37

10140010010155005

13135025

00012015010100150

3015151515603010K45

Min.

50843040812008081350 0 5

Max.

10K

Max.

10K

Unit

nsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsns

Notes

tCL1RH1(R)tRSHtCH2RL2tCH2WXtRH2WXtCL1tGL1QVtCL1QVtRL1QVtAVQVtCL1QXtCH2QXtCL1QZtRL1AVtGL2QZtWL1CH1tWL1CL2tCL1WH1tWL1WH1tGL1QZtWL1RH1tDVWL2

tCRPtRCHtRRHtCOHtOACtCACtRACtCAAtCLZtOFFtDZCtRADtOEZtCWLtWCStWCHtWPtDEOtRWLtDS

99

7, 127, 127, 137

15

8

11

15

10

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AC Characteristics (Cont’d)

JEDEC

SymbolSymbol

tWL1DXtWL1GL2tCH2RH2tRL2RL2(RMW)tCL1WL2tRL1WL2tAVWL2tCL2CL2tCH2CL2tAVRH1tCH2QVtCL1RL2tRH2CL2tRL1CH1tRH2CL2tRH2CL2tRH2CL2tRH2CL2tRH2CL2tRH2CL2tRH2CL2tRH2CL2tT

tDHtWOHtPRWCtRWCtCWDtRWDtAWDtPCtCPtCARtCAPtCSRtRPCtCHRtRASPtRHCPtCPWDtCPTtWRPtWRHtCDDtODDtTtREF

V53C516165A50

Parameter

Data in Hold TimeWrite to OE Hold TimeEDO Page Mode Read-Write Cycle TimeRead-Modify-Write Cycle TimeCAS to WE DelayRAS to WE Delay in Read-Modify-Write Cycle Column Address to WE DelayEDO Page Mode Read or Write Cycle TimeCAS Precharge TimeColumn Address to RAS Setup TimeAccess Time from Column PrechargeCAS Setup Time CAS-before-RAS Refresh

RAS to CAS Precharge TimeCAS Hold Time CAS-before-RAS RefreshRAS Pulse Width (EDO Mode)CAS Precharge Time to RAS DelayCAS Precharge Time to WECAS Precharge Time (CBR Counter Test)Write to RAS Precharge time (CRB Cycle)Write Hold time reference to RAS (CRB Cycle)

CAS High to Data delayOE High to Data delayTransition Time (Rise and Fall)Refresh Interval (4096 Cycles)

1051050274135101010101

50200K

60Min.

101368138327747251030

27

1051060324940101013131

50200K32

Min.

81058113273920825

Max.Max.Unit

nsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsms

Notes

1010

101010

6

1616

Self Refresh AC CharacteristicstRASStRPStCHStREF

RAS Pulse Width During Self RefreshRAS Precharge Time During Self RefreshCAS Hold Time Width During Self RerfreshRefresh period for L-Version

100K9550

256

100K11050

256

nsnsnsms

171717

V53C516165A Rev. 1.0 March 1998

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Notes: 1. All voltage are referenced to VSS.

2.ICC1, ICC3, ICC4, and ICC7 depend on cycle rate.

3.ICC1 and ICC4 depend on output loading. Specified values are measured with the output open.

V53C516165A4.Address can be changed once or less while RAS = VIL. In the case of ICC4 it can be changed once or less during

an EDO cycle (tHPC).5.An initial pause of 200 µs is required after power-up followed by 8 RAS cycles of which at least one cycle has to bea refresh cycle, before proper device operation is achieved. In case of using internal refresh counter, a minimum of8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required.6.VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are also mea-sured between VIH and VIL.7.Measured with a load equivalent to 2 TTL gates and 50 pF (VOL = 0.8V and VOH = 2.0V).

8.tOFF (max.) and tOEZ (max.) define the time at which the outputs acheive the open-circuit condition and are not ref-erenced to output voltage levels.9.Either tRCH or tRRH must be satisfied for a read cycle.

10.These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge in read-write cycles.11.tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as

electrical characteristics only. If tWCS > tWCS (min.), the cycle is an early write cycle and the I/O pin will remain open-circuit (high impedance) through the entire cycle; if tRWD > tRWD (min.), tCWD > tCWD (min.), tAWD > tAWD (min.), andtCPWD > tCPWD (min.), the cycle is a read-write cycle and I/O pins will contain data read from the selected cells. Ifneither of the above sets of conditions is satisfied, the condition of the I/O pins (at access time) is indeterminate.12.Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a reference

point only: if tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by tCAC.13.Operation within the tRAD (max) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference

point only: if tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by tCAA.14.AC measurements assume tT = 2 ns.15.Either tDZC or tDEO must be satisfied.16.Either tCDD or tODD must be satisfied.

17.When using Self Refresh mode, the following refresh operations must be performed to ensure proper DRAM oper-ation:

If row addresses are being refreshed on an evenly distributed manner over the refresh interval using CBR refreshcycles, then only one CBR cycle must be performed immediately after exit from Self Refresh.

If row addresses are being refreshed in any other manner (ROR – Distributed/Burst; or CBR – Burst) over the re-fresh interval, then a full set of row refreshes must be performed immediately before entry to and immediately afterexit from Self Refresh.

18.tOFF is referenced from the rising edge of RAS or CAS, whichever occurs last.V53C516165A Rev. 1.0 March 1998

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Waveforms of Read Cycle tRCtRASVIH

RASVIL

tRCDUCASLCASVIHVIL

tASRVIH

Address

VIL

RowColumntRCHtRAHVIH

WEVIL

tCAAtOACtRCStRRHRowtCSHtRSHtCAStRADtASCtCAHtCRPtRPV53C516165AtCARtASRVIH

OEVIL

tDZCtDZOtCDDtODDI/O

(Inputs)

VIHVIL

tCACtOEZValid Data OuttRACtOFFI/O

(Outputs)

VOHVOLHi ZtCLZHi Z“H” or “L”

511816502-04

V53C516165A Rev. 1.0 March 1998

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Waveforms of Write Cycle (Early Write) tRCtRASVIH

RASVIL

tRCDUCASLCASVIHVIL

tRADtASRVIH

Address

VIL

RowColumntCWLtWCStWPtASCtCAHtCARtASRtCSHtRSHtCAStCRPtRPV53C516165A.RowtRAHVIH

WEVIL

tWCHtRWLVIH

OEVIL

tDHtDSI/O

(Inputs)

VIH

Valid Data InVIL

I/O

(Outputs)

VOH

Hi ZVOL

“H” or “L”

511816502-05

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Waveforms of Write Cycle (OE Controlled Write) tRCtRASVIH

RASVIL

tRCD V53C516165AtRPtCSHtRSHtCAStCRPUCASLCASVIHVIL

tRADtASRVIH

RowtASCtCAHtCARtASRRowtCWLAddress

VIL

ColumntRAHVIH

WEVIL

tRWLtWPtOEHVIH

OEVIL

tDZOtDZCI/O

(Inputs)

VIHVIL

Valid DatatCLZtOACVOHI/O

(Outputs)

Hi-ZVOLHi-ZtOEZtODDtDHtDS“H” or “L”

511816502-06

V53C516165A Rev. 1.0 March 1998

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MOSEL VITELIC

Waveforms of Read-Write (Read-Modify-Write) Cycle tRWCtRASVIHVIL

tCSHtRCDUCASLCASVIHVIL

tRAHtASRAddress

VIH

RowVIL

tRADtAWDtCWDtRWDVIH

WEVIL

tCAAtRCSVIH

OEVIL

tDZOtDZCVIH

I/O

(Inputs)

VIL

tCLZtCACtOEZI/O

(Outputs)

VOHVOL

tRAC“H” or “L”

V53C516165AtRPRAStRSHtCAStCRPtCAHtASCtASRColumntCWLtRWLtWPRowtOACtOEHtDStDHValidData intODDData Out511816502-07

V53C516165A Rev. 1.0 March 1998

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Waveforms of EDO Page Mode Read Cycle V53C516165AtRASPVIH

tRPRAStRCDtRHPCVIL

tCRPUCASLCASVIHVIL

tPCtCAStCPtCAStRSHtCAStCRPtCSHtASRtRAHtASCtCAHtASCtCAHtCARtASCtCAHVIH

Address

VIL

RowtRADColumn 1Column 2Column NtRRHtRCSVIH

tRCHWEVIL

tCACtCAAtOEStCPAtCACtCAAtCPAtOFFVOH

tOACOEVOL

tRACtCAAtCACVIHVIL

tOEZtCOHtCOHtCLZData Out1Data Out2Data OutNI/O (Output)

511816502-08

“H” or “L”

V53C516165A Rev. 1.0 March 1998

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Waveforms of EDO Page Mode Read Cycle (OE Control) V53C516165AtRASPVIH

tRPtRCDtRHPCRASVIL

tPCtCRPVIH

tRSHtCPtCAStCAStCRPtCASUCASLCASVIL

tCSHtRAHtASCtCAHtASCtCAHtASCtCARtCAHtASRVIH

Address

VIL

RowtRADColumn 1Column 2Column NtRRHtRCSVIH

tRCHWEVIL

tCACtCAAtOEStOEHCtCPAtOEHCtCACtCAAtCPAtOFFVOHtOACOEVOLtRACtCAAtCACVIHVIL

tOEPtOEZtOACtOEPtOACtOEZtOEZtCLZData Out1Data Out2Data OutNI/O (Output)

“H” or “L”

511816502-09

V53C516165A Rev. 1.0 March 1998

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Waveforms of EDO Page Mode Read Cycle (WE Control) tRASPVIH

V53C516165AtRPRAStRCDtRHPCVIL

tPCtCRPUCASLCASVIHVIL

tRSHtCPtCAStCAStCRPtCAStCSHtRAHtASCtCAHtASCtCAHtASCtCARtCAHtASRAddress

VIH

RowVIL

Column 1Column 2tCAAColumn NtCAAtRRHtRADtRCSVIH

tRCHtRCStRCHtRCStRCHWEVIL

tWPZtCACtOESVOHtWPZtCACtCPAtOFFtCPAtOACOEVOLtCARtCAAtCACVIHVIL

tOEZtWEZtWEZtCLZData Out1Data Out2Data OutNI/O (Output)

“H” or “L”

511816502-10

V53C516165A Rev. 1.0 March 1998

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Waveforms of EDO Page Mode Early Write Cycle V53C516165AtRASPVIH

tRPtRCDtRHPCRASVIL

tCRPUCASLCASVIHVIL

tPCtCAStCPtCAStRSHtCAStCRPtCSHtASRtRAHtASCRowAddrtRADtCWLtWCStWCHtWPtWCStCWLtWCHtWPtWCStCAHtASCtCAHtASCtCARtCAHVIH

Address

VIL

Column 1Column 2Column NtRWLtCWLtWCHtWPVIH

WEVIL

VOHOEVOLtDSVIH

tDHtDStDHtDStDHI/O (Input)

VIL

Data In 1Data In 2Data In N“H” or “L”

511816502-11

V53C516165A Rev. 1.0 March 1998

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Waveforms of EDO Page Mode Late Write Cycle V53C516165AtRASPVIH

tRPRAStRCDtCRPVIL

tPCtCRPUCASLCASVIHVIL

tRSHtCPtCAStCPtCAStCAStCSHtRAHtASCtCAHtASCtCAHtCARtASCtCAHtASRVIH

Address

VIL

RowtRADColumn 1tCWLColumn 2tCWLColumn NtCWLtRWLtRCSVIH

tRCStRCSWEVIL

tWPtWPtWPtOEHVOHtOEHtOEHOEVOLtODDtDStODDtODDtDStDHtDStDHtDHI/O (Input)

VIHVIL

Data In1Data In2Data InN“H” or “L”

511816502-12

V53C516165A Rev. 1.0 March 1998

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tRASPVIHRAStCSHtRCDtCAStCAStCARtASRtCAStRADtRAHtASCtASCColumntCPWDtCWDtCWLtCPWDtCWDtRWLtCWLtAWDtWPtOACtWPColumntRCStAWDtWPtOACtAWDtRWDtCWDtCWLColumntASCtCAHtCAHtCAHtCRPtCPtPRWCtRSHtRP元器件交易网www.cecb2b.com

V53C516165A Rev. 1.0 March 1998

MOSEL VITELIC

VILUCASLCASVIHVILtASRVIHAddressRowRowVILVIHWEtCAAtOACWaveforms of EDO Page Mode Read-Modify-Write Cycle 17

tDZCtCLZtDZCData IntCLZtCACtRACtOEZtDHtDSDataOutDataOutVILVIHOEtCPAtODDVILtCPAtDZCData IntCLZtOEHVIHtDZOtODDData IntOEHI/O(Inputs)tODDtOEHtCAAVILtOEZtDStDHtCAAtCACtOEZtDSDataOuttDHI/O(Outputs)VOHVOLV53C516165A511816502-13元器件交易网www.cecb2b.com

MOSEL VITELIC

Waveforms of RAS Only Refresh CycletRCtRASRASVIHVIL

V53C516165AtRPtRPCUCASLCASVIHVIL

tCRPtRAHtASRtASRVIH

Address

VIL

RowRowI/O

(Outputs)

VOH

HI-ZVOL

511816502-14

“H” or “L”

V53C516165A Rev. 1.0 March 1998

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MOSEL VITELIC

Waveforms of CAS-before-RAS Refresh Cycle tRCtRPVIHV53C516165AtRAStRPRASVIL

tRPCtCPUCASLCASVIHVIL

tCRPtCSRtCHRtRPCtWRPtWRHVIHWEVIL

tOEZVIHOEVIL

tCDDVIHVIL

I/O

(Inputs)

tODDI/O

(Outputs)

VOHHI-ZVOLtOFF511816502-15

“H” or “L”

V53C516165A Rev. 1.0 March 1998

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MOSEL VITELIC

Waveforms of CAS-before-RAS Self Refresh Cycle (Optional) V53C516165AtRPVIHtRASStRPSRASVIL

tRPCtCPUCASLCASVIHVIL

tCSRtCRPtCHStWRPtWRHVIHWEVIL

VIHOEVIL

tCDDVIHVIL

I/O

(Inputs)

tODDtOEZI/O

(Outputs)

VOHHI-ZVOLtOFF511816502-15

“H” or “L”

V53C516165A Rev. 1.0 March 1998

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MOSEL VITELIC

Waveforms of Hidden Refresh Read Cycle tRCtRAStRPtRCtRASV53C516165AtRPVIHRASVIL

tRCDtRSHtCHRtCRPUCASLCASVIHVIL

tRADtASCtRAHtASRtCAHColumntWRPtWRHtASRVIHAddress

VIL

RowRowtRCSVIHtRRHWEVIL

tCAAtOACVIHOEVIL

tDZCtDZOtCDDtODDI/O

(Inputs)

VIHVIL

tCACtCLZtRACtOEZtOFFI/O

(Outputs)

VOHVOLValid Data OutHI-Z“H” or “L”

511816502-16

V53C516165A Rev. 1.0 March 1998

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MOSEL VITELIC

Waveforms of Hidden Refresh Early Write CycletRCtRPVIHV53C516165AtRCtRAStRPtRASRASVILtRCDVIHVILtRSHtCHRtCRPUCASLCAStRADtRAHtASRtASCtCAHColumntWCStWCHtWRPtWRHtASRVIHAddress

VILRowRowVIHtWPWEVILtDSVIHtDH I/O(Input)

Valid DataVIL I/O

(Output)

VOHHI-ZVOL

511816502-17

“H” or “L”

V53C516165A Rev. 1.0 March 1998

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Functional DescriptionThe V53C516165A is a CMOS dynamic RAM op-timized for high data bandwidth, low power applica-tions. It is functionally similar to a traditionaldynamic RAM. The V53C516165A reads and writesdata by multiplexing an 20-bit address into a 12-bitrow and a 8-bit column address. The row address islatched by the Row Address Strobe (RAS). The col-umn address “flows through” an internal addressbuffer and is latched by the Column Address Strobe(CAS). Because access time is primarily dependenton a valid column address rather than the precisetime that the CAS edge occurs, the delay time fromRAS to CAS has little effect on the access time.V53C516165Aaccessed at a high data rate. Maintaining RAS lowwhile performing successive CAS cycles retains therow address internally and eliminates the need toreapply it for each cycle. The column address bufferacts as a transparent or flow-through latch whileCAS is high. Thus, access begins from the occur-rence of a valid column address rather than from thefalling edge of CAS, eliminating tASC and tT from thecritical timing path. CAS latches the address into thecolumn address buffer. During EDO operation,Read, Write, Read-Modify-Write or Read-Write-Read cycles are possible at random addresseswithin a row. Following the initial entry cycle intoEDO Mode, access is tCAA or tCAP controlled. If thecolumn address is valid prior to the rising edge ofCAS, the access time is referenced to the CAS ris-ing edge and is specified by tCAP. If the column ad-dress is valid after the rising CAS edge, access istimed from the occurrence of a valid address and isspecified by tCAA. In both cases, the falling edge ofCAS latches the address and enables the output.EDO provides a sustained data rate of 50 MHz forapplications that require high bandwidth such as bit-mapped graphics or high-speed signal process-ing. The following equation can be used to calculatethe maximum data rate:

4096

Data Rate=-------------------------------------------tRC+4095×tPC

Memory CycleA memory cycle is initiated by bringing RAS low.Any memory cycle, once initiated, must not be end-ed or aborted before the minimum tRAS time has ex-pired. This ensures proper device operation anddata integrity. A new cycle must not be initiated untilthe minimum precharge time tRP/tCP has elapsed.

Read CycleA Read cycle is performed by holding the WriteEnable (WE) signal High during a RAS/CAS opera-tion. The column address must be held for a mini-mum specified by tAR. Data Out becomes valid onlywhen tOAC, tRAC, tCAA and tCAC are all satisifed. Asa result, the access time is dependent on the timingrelationships between these parameters. For exam-ple, the access time is limited by tCAA when tRAC,tCAC and tOAC are all satisfied.

Self RefreshSelf Refresh mode provides internal refresh con-trol signals to the DRAM during extended periods ofinactivity. Device operation in this mode providesadditional power savings and design ease by elimi-nation of external refresh control signals. Self Re-fresh mode is initialed with a CAS before RAS(CBR) Refresh cycle, holding both RAS low (tRASS)and CAS low (tCHD) for a specified period. Both ofthese parameters are specified with minimum val-ues to guarantee entry into Self Refresh operation.Once the device has been placed in to Self Refreshmode the CAS clock is no longer required to main-tain Self Refresh operation.

The Self Refresh mode is terminated by returningthe RAS clock to a high level for a specified (tRPS)minimum time. After termination of the Self Refreshcycle normal accesses to the device may be initiat-ed immediately, poviding that subsequest refreshcycles utilize the CAS before RAS (CBR) mode ofoperation.

Write CycleA Write Cycle is performed by taking WE andCAS low during a RAS operation. The column ad-dress is latched by CAS. The Write Cycle can beWE controlled or CAS controlled depending onwhether WE or CAS falls later. Consequently, theinput data must be valid at or before the falling edgeof WE or CAS, whichever occurs last. In the CAS-controlled Write Cycle, when the leading edge ofWE occurs prior to the CAS low transition, the I/Odata pins will be in the High-Z state at the beginningof the Write function. Ending the Write with RAS orCAS will maintain the output in the High-Z state.In the WE controlled Write Cycle, OE must be inthe high state and tOED must be satisfied.

Extended Data Output Page Mode EDO Page operation permits all 4096 columnswithin a selected row of the device to be randomly

V53C516165A Rev. 1.0 March 1998

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Data Output OperationThe V53C516165A Input/Output is controlled byOE, CAS, WE and RAS. A RAS low transition en-ables the transfer of data to and from the selectedrow address in the Memory Array. A RAS high tran-sition disables data transfer and latches the outputdata if the output is enabled. After a memory cycleis initiated with a RAS low transition, a CAS lowtransition or CAS low level enables the internal I/Opath. A CAS high transition or a CAS high level dis-ables the I/O path and the output driver if it is en-abled. A CAS low transition while RAS is high hasno effect on the I/O data path or on the output driv-ers. The output drivers, when otherwise enabled,can be disabled by holding OE high. The OE signalhas no effect on any data stored in the output latch-es. A WE low level can also disable the output driv-ers when CAS is low. During a Write cycle, if WEgoes low at a time in relationship to CAS that wouldnormally cause the outputs to be active, it is neces-sary to use OE to disable the output drivers prior tothe WE low transition to allow Data In Setup Time(tDS) to be satisfied.

V53C516165ADuring Power-On, the VCC current requirement ofthe V53C516165A is dependent on the input levelsof RAS and CAS. If RAS is low during Power-On,the device will go into an active cycle and ICC will ex-hibit current transients. It is recommended that RASand CAS track with VCC or be held at a valid VIH dur-ing Power-On to avoid current surges.

Table 1. V53C516165A Data OutputOperation for Various Cycle TypesCycle Type

Read Cycles

CAS-Controlled Write Cycle (Early Write)WE-Controlled WriteCycle (Late Write)Read-Modify-Write CyclesEDO Read Cycle

EDO Write Cycle (Early Write)

I/O State

Data from AddressedMemory CellHigh-Z

OE Controlled. HighOE = High-Z I/OsData from AddressedMemory CellData from AddressedMemory CellHigh-Z

Data from AddressedMemory CellHigh-ZHigh-ZHigh-Z

Power-OnAfter application of the VCC supply, an initialpause of 200 µs is required followed by a minimumof 8 initialization cycles (any combination of cyclescontaining a RAS clock). Eight initialization cyclesare required after extended periods of bias withoutclocks (greater than the Refresh Interval).

EDO Read-Modify-Write CycleRAS-only RefreshCAS-before-RASRefresh CycleCAS-only CyclesV53C516165A Rev. 1.0 March 1998

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Package Diagrams42-Pin 400 mil SOJ

1.08 –0.010 [27.41 –0.25]4222.441 –0.006 [11.2 –0.15](1)0.370±0.010 [9.4±0.25].441 ±0.006 [11.2 ±0.15]V53C516165A.406 –0.012 [10.3 –0.3]1210.045 [1.15] MIN.406 –0.012(1)[10.3 – 0.3]0.008–0.0020.088 ±0.004 [2.24 ±0.1]+0.005+0.120.2–0.050.81 [.032] MAX0.017±0.004 [0.43 ±0.1]0.05 [1.27]1.0 [25.4]0.145 [3.68] MAX0.004 [0.1]Unit in inches [mm](1) Does not include plastic or metal protrusion of 0.010 [0.25] max per side.50/44-Pin 400 mil TSOP-II

0.039 ± 0.002[1 ± 0.05]0.004±0.002[0.1±0.05]0.047 Max[1.2 Max]0.4 ± 0.005[10.16 ± 0.13]0.006–0.0010.15–0.03+0.08+0.0030.031 [0.8]0.016+0.002–0.0040.4+0.05–0.1504036260.008 [0.2]M44x0.004 [0.1]0.020±0.004[0.5 ± 0.1]0.463±0.008[11.76 ± 0.2]11115125Unit in inches [mm]0.825±0.005[20.95±0.13]1Does not include plastic or metal protrusion of 0.010 [0.25] max. per sideV53C516165A Rev. 1.0 March 1998

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NotesV53C516165A Rev. 1.0 March 1998

V53C516165A26

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NotesV53C516165A Rev. 1.0 March 1998

V53C516165A27

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