Method and system for eliminating extrusions in se

专利名称：Method and system for eliminating

extrusions in semiconductor vias

发明人：Steven Mark Anderson,Siddhartha

Bhowmik,Joseph William Buckfeller,SaileshMansinh Merchant,Frank Minardi

申请号：US10713524申请日：20031112

公开号：US20040106279A1公开日：20040603

专利附图：

摘要：A system and method for eliminating interconnect extrusions in vias that are

formed during ionized metal plasma processing. By eliminating interconnect extrusions invias, reliability failures and yield loss are decreased. The extrusions of interconnectmetallization occur while wafers are subject to elevated temperatures that cause theinternal stresses in the interconnect metallization to transit from a substantially tensilemode to a substantially compressive mode. By controlling the interconnect temperatureto be below the temperature at which the interconnect transits from a tensile to acompressive mode, interconnect extrusions in vias are eliminated. The interconnecttemperature is controlled by using an actively cooled pedestal in combination with a lowtemperature IMP deposition process. In addition, the IMP processing time may also bedecreased to limit heating of the interconnect.

申请人：ANDERSON STEVEN MARK,BHOWMIK SIDDHARTHA,BUCKFELLER JOSEPHWILLIAM,MERCHANT SAILESH MANSINH,MINARDI FRANK

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