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Implementation Agreement: OIF-TFI5-0.1.0 TFI-5 TDM Fabric to Framer Interface

TFI-5: TDM Fabric to Framer Interface Implementation Agreement

OIF-TFI-5-01.0

September 16, 2003

Implementation Agreement Created and Approved

by the Optical Internetworking Forum

www.oiforum.com

Optical Internetworking Forum 1

Implementation Agreement: OIF-TFI5-0.1.0 TFI-5 TDM Fabric to Framer Interface

Contribution Number: oif2002.287.17

Working Group: Physical and Link Layer

TITLE: TFI-5: TDM Fabric to Framer Interface Implementation Agreement

DATE: September 16, 2003

SOURCE:

Brian Von Herzen TFI-5 Technical Editor Xilinx, Inc./FPGA.com 675 Fairview Drive, #246 Carson City, NV 701 Phone: +1 775 790-5000 Email:Brian@FPGA.com Mike Lerer PLL Chair

Xilinx, Inc./FPGA.com Box 636

Londonderry, NH 03053 Phone: +1 603 8 3704

Email: mlerer@fpga.com

Karl Gass

PLL Vice Chair

Sandia National Laboratories PO Box 5800, MS 0874 Albuquerque, NM 87185 Phone: +1 505 844-8849 Email: kgass@sandia.gov

________________________________________________________________ Document Status: Approved IA Project Name: TFI 5

ABSTRACT: This IA lists objectives for TFI-5 connects TDM fabrics to SONET/SDH and

OTN Framers (TDM Fabric to Framer Interface or TFI-5), with line-side interface rates of up to OC-768, STM-256 or OTU-3. The interface supports synchronous time-division multiplexed switches that have a minimum granularity of STS-1 and above.

Notice: This Technical Document has been created by the Optical Internetworking Forum (OIF).

This document is offered to the OIF Membership solely as a basis for agreement and is not a binding proposal on the companies listed as resources above. The OIF reserves the rights to at any time to add, amend, or withdraw statements contained herein. Nothing in this document is in any way binding on the OIF or any of its members.

The user's attention is called to the possibility that implementation of the OIF implementation agreement contained herein may require the use of inventions covered by the patent rights held by third parties. By publication of this OIF implementation agreement, the OIF makes no

representation or warranty whatsoever, whether expressed or implied, that implementation of the specification will not infringe any third party rights, nor does the OIF make any representation or warranty whatsoever, whether expressed or implied, with respect to any claim that has been or may be asserted by any third party, the validity of any patent rights related to any such claim, or the extent to which a license to use any such rights may or may not be available or the terms hereof.

For additional information contact:

The Optical Internetworking Forum, 39355 California Street,

Suite 307, Fremont, CA 94538

510-608-5928 phone, info@oiforum.com

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Implementation Agreement: OIF-TFI5-0.1.0 TFI-5 TDM Fabric to Framer Interface

This document and translations of it may be copied and furnished to others, and derivative works that comment on or otherwise explain it or assist in its implementation may be prepared, copied, published and distributed, in whole or in part, without restriction other than the following, (1) the above copyright notice and this paragraph must be included on all such copies and derivative works, and (2) this document itself may not be modified in any way, such as by removing the copyright notice or references to the OIF, except as needed for the purpose of developing OIF Implementation Agreements.

By downloading, copying, or using this document in any manner, the user consents to the terms and conditions of this notice. Unless the terms and conditions of this notice are breached by the user, the limited permissions granted above are perpetual and will not be revoked by the OIF or its successors or assigns.

This document and the information contained herein is provided on an \"AS IS\" basis and THE OIF DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO ANY WARRANTY THAT THE USE OF THE INFORMATION HEREIN WILL NOT INFRINGE ANY RIGHTS OR ANY IMPLIED WARRANTIES OF MERCHANTABILITY, TITLE OR FITNESS

FOR A PARTICULAR PURPOSE.

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Implementation Agreement: OIF-TFI5-0.1.0 TFI-5 TDM Fabric to Framer Interface

1. Table of Contents

0. Cover Sheet................................................................................................1 1. 2. 3. 4. 5. 6. 7. 8. 9.

TABLE OF CONTENTS...............................................................................4 LIST OF FIGURES.......................................................................................6 LIST OF TABLES........................................................................................7 DOCUMENT REVISION HISTORY..............................................................8 REFERENCES...........................................................................................10 INTRODUCTION........................................................................................11 REQUIREMENTS......................................................................................12 INTERFACE DEFINITION..........................................................................14 SIGNAL DEFINITION................................................................................16

10. DETAILED DESCRIPTION........................................................................18

10.1 TFI-5 Link Layer.................................................................................22

10.2 TFI-5 Connection Layer......................................................................25 10.3 TFI-5 Mapping Layer..........................................................................27 11. ELECTRICAL INTERFACE DEFINITION..................................................40

11.1 Differential Output Characteristics......................................................41 11.2 Differential Input Characteristics.........................................................43 11.3 Jitter Requirements............................................................................46 11.4 Wander Requirements.......................................................................47 12. OPTICAL INTERFACE DEFINITION.........................................................49

12.1 Optical cable, cable plant specification and link budget......................51 APPENDIX A: MAPPING AND TRANSPORT OF ODU3 AND 10GIGE LAN PHY 52

A.1 Asynchronous mapping of ODU3 into a C-4-272c for transport over 272 VC-4 / STS-3c’s..........................................................................................52 A.2 Mapping of 10GE LAN PHY.................................................................57 APPENDIX B: JITTER NOTES..........................................................................63 APPENDIX C

SAMPLE APPLICATION.......................................................

C.1 STS-1 Cross-connect........................................................................ APPENDIX D: INTER-CONNECT CHARACTERISTICS...................................66

Connector Impedance................................................................................66 Optical Internetworking Forum

Implementation Agreement: OIF-TFI5-0.1.0 TFI-5 TDM Fabric to Framer Interface

Characteristic Impedance...........................................................................66 Channel Model...........................................................................................66 APPENDIX E: CROSS TALK.............................................................................69 APPENDIX F: TERMS AND DEFINITIONS GLOSSARY..................................70

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Implementation Agreement: OIF-TFI5-0.1.0 TFI-5 TDM Fabric to Framer Interface

2. List of Figures

FIGURE 8.1 TFI-5 SYSTEM REFERENCE MODEL.......................................................14 FIGURE 10.2 TFI-5 2.488 GBPS (STS-48) FRAME FORMAT (REQUIRED SUPPORT).....19 FIGURE 10.3 TFI-5 3.1104 GBPS (STS-60) FRAME FORMAT (OPTIONAL SUPPORT)...19 FIGURE 10.4 TFI-5 LAYERS...................................................................................20 FIGURE 10.5 TFI-5 LAYERS EXAMPLE (AN STS-1 CROSS-CONNECT).........................21 FIGURE 10.5.1 TFI-5 STATE DIAGRAM FOR OUT OF FRAME AND IN FRAME CONDITIONS

.....................................................................................................................23 FIGURE 10.5.2 TFI-5 FRAME OFFSET TIMING...........................................................25 FIGURE 10.6 TFI-5 CONNECTION MONITORING (CM) MULTI-FRAME FORMAT..............26 FIGURE 10.7 EXAMPLE DISINTERLEAVING SHOWING BYTE ORDERING OF AN STS-768

FRAME INTO 16 TFI-5 LINKS............................................................................30 FIGURE 10.8 EXAMPLE OF DISINTERLEAVING SHOWING BYTE ORDERING OF AN STS-192

FRAME INTO 4 TFI-5 LINKS..............................................................................31 FIGURE 11.1 TFI-5 APPLICATION MODEL FOR THE PURE ELECTRICAL INTERFACE, ALSO

CALLED THE INTRA-RACK SYSTEM.....................................................................40 FIGURE 11.2 GENERAL SIGNAL DEFINITION.............................................................40 FIGURE 11.3 TERMINATION AND SIGNALING.............................................................44 FIGURE 11.4 IDSHORT, IOFF & VRPP TESTING.........................................................45 FIGURE 11.5 RECEIVE EYE MASK...........................................................................47 FIGURE 11.6 SINUSOIDAL JITTER ALLOWABLE AMPLITUDE VS. FREQUENCY. NOTE THAT

RELATIVE WANDER FROM ONE LANE TO ANOTHER CAN BE TWICE THE ABSOLUTE

WANDER OF 32 UI SHOWN IN THIS DIAGRAM......................................................48 FIGURE 12.1: ELECTRO-OPTICAL INTER-RACK APPLICATION MODEL...........................49 FIGURE 12.2 FIBER OPTIC CABLING MODEL..............................................................51 FIGURE A.1: BLOCK STRUCTURE FOR ODU3 MAPPING INTO C-4-272C...................... FIGURE A.2: MAPPING OF ODU3 OVER C-4-272C FOR TRANSPORT OVER 272 VC-4’S55 FIGURE A.3: DEMAPPING OF AN ODU3 FROM A C-4-272C TRANSPORTED OVER 272

VC-4’S..........................................................................................................56 FIGURE A.4: BLOCK STRUCTURE FOR 10GE LAN PHY MAPPING INTO C-4-70C.........60 FIGURE A.5: MAPPING OF 10GE LAN PHY OVER C-4-70C FOR TRANSPORT OVER 70

VC-4’S..........................................................................................................61 FIGURE A.6: DEMAPPING OF 10GE LAN PHY FROM A C-4-70C TRANSPORTED OVER 70

VC-4’S..........................................................................................................62 FIGURE C.1: STS-1 CROSS-CONNECT EXAMPLE..................................................... FIGURE D.1 CHANNEL MODELS..............................................................................68

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Implementation Agreement: OIF-TFI5-0.1.0 TFI-5 TDM Fabric to Framer Interface

3. List of Tables

Table 9.1 TFI-5 Signal Summary................................................................16 Table 10.1 Layer Assignments of TFI-5 bytes............................................28 Table 10.2 Client Status Indication (CSI) Coding for SONET/SDH clients.32 Table 10.3 Transport of OTN entities over TFI-5 link(s) via STS-3c/VC-4 Time-slots...................................................................................................33 Table 10.4: Client Status Indication (CSI) Coding for OTN clients.............38 Table 11.2: TFI-5 Differential Input Characteristics....................................43 Table 11.3: Receive Eye Mask Specifications............................................47 Table 12.1 Optical Interface Specifications................................................50 Table 12.2 Multimode cable link power budget..........................................51 Table A.1: Mapping of 10GE LAN PHY: format and efficiency...................57 Table A.2: Mapping of 10GELAN PHY: rate adaptation.............................57 Table A.3: : Client Status Indication (CSI) Coding for 10GE LAN PHY

clients.........................................................................................................59 Table B.1: Jitter budget for electrical intra-rack and electro-optical inter-rack applications................................................................................................63

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Implementation Agreement: OIF-TFI5-0.1.0 TFI-5 TDM Fabric to Framer Interface

4. Document Revision History

oif2002.287.00 19 May 2002 TFI-5 working group selected

proposal OIF2002.122.2 as the Baseline document for TFI-5 from April 2002 OIF Plenary Meeting in Boston, MA.

oif2002.287.01 No significant changes. oif2002.287.02 13 July 2002 TFI-5 Implementation Agreement Draft

1.1. Document revised to incorporate editorial and technical changes from the June 2002 TFI-5 Interim Meeting in San Jose, CA.

oif2002.287.03: 01 Aug 2002 TFI-5 Implementation Agreement Draft

1.2. Document revised to incorporate editorial and technical

changes from the July 30-Aug1 2002 OIF Meeting in Copenhagen DK.

oif2002.287.04: Marked changes accepted after TFI-5 straw ballot.

oif2002. 287.05 7 November 2002 TFI-5 Implementation Agreement Draft

1.3. Document revised to incorporate editorial changes from comments received from Straw Ballot #33. clean version

oif2002. 287.06 7 November 2002 TFI-5 Implementation Agreement Draft

1.3. Same version as .05 but with change bars and changes highlighted.

oif2002. 287.07 17 November 2002 TFI-5 Implementation Agreement Draft

1.4. Document revised to incorporate changes from the November 2002 TFI-5 Plenary Meeting in Orlando, FL.

oif2002. 287.08 20 December 2002 TFI-5 Implementation Agreement Draft

1.5. Document revised to incorporate changes from the Straw Ballot of December 16, 2002.

oif2002. 287.09 20 December 2002 TFI-5 Implementation Agreement Draft

1.5. Document revised to incorporate editorial changes from the TFI-5 conference call on December 20, 2002.

oif2002. 287.10 12 February 2003 TFI-5 Implementation Agreement Draft

10. Document revised to incorporate technical changes from the TFI-5 interim meeting on 10 February 2003 and changes from the Los Angeles Plenary in February 2003. Optical Internetworking Forum

Implementation Agreement: OIF-TFI5-0.1.0 TFI-5 TDM Fabric to Framer Interface

oif2002. 287.11 26 April 2003 TFI-5 Implementation Agreement Draft 11.

Document revised to incorporate editorial and technical changes from the TFI-5 conference call on March 28 2003.

oif2002. 287.12 6 May 2003 TFI-5 Implementation Agreement Draft 12.

Document revised to incorporate technical change from the TFI-5 receiver sensitivity ad-hoc conference calls of March and April, 2003.

oif2002. 287.13 4 July 2003 TFI-5 Implementation Agreement Draft 13.

Document revised to incorporate technical changes from the TFI-5 Scottsdale Plenary in April 2003.

oif2002. 287.14 29 July 2003 TFI-5 Implementation Agreement Draft 14.

Document revised to incorporate editorial changes from the TFI-5 Straw Ballot #43.

oif2002. 287.15 29 July 2003 TFI-5 Implementation Agreement Draft 15,

Updated list of figures.

oif2002. 287.16 29 July 2003 TFI-5 Implementation Agreement Draft 16,

Updated appendix D labels.

oif2002. 287.17 6 August 2003 TFI-5 Implementation Agreement Draft

17, minor editorial changes.

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Implementation Agreement: OIF-TFI5-0.1.0 TFI-5 TDM Fabric to Framer Interface

5. References

[1] Optical Internetworking Forum, OIF2001.149.14, “SxI-5: Electrical Characteristics of Common I/O for SFI-5 and SPI-5”, November 2002.

[2] Optical Internetworking Forum, OIF-SFI5-01.0 - SerDes Framer Interface Level 5 (SFI-5): 40Gbps Interface for Physical Layer Devices.

[3] Optical Internetworking Forum, OIF-SPI5-01.1 - System Packet Interface Level 5 (SPI-5): OC-768 System Interface for Physical and Link Layer Devices.

[4] Telcordia, GR-253-CORE, Issue 3 Sept. 2000 – “Synchronous Optical Network (SONET) Transport System: Common Generic Criteria”

[5] ITU-T, Recommendation G.707, Oct. 2000 – \"Network Node Interface For The Synchronous Digital Hierarchy (SDH)\"

[6] ITU-T, Recommendation G.709, Feb. 2001 – “Network Node Interface for the Optical Transport Network (OTN)”

[7] ITU-T, Recommendation G.707, Amendment 2, 2002 – \"Network Node Interface For The Synchronous Digital Hierarchy (SDH), Amendment 2\"

[8] IEEE, 802.3ae-2002, “Information Technology - Local & Metropolitan Area Networks - Part 3: Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer Specifications - Media

Access Control Parameters, Physical Layers and Management Parameters for 10 Gb/s Operation”

[9] ANSI; T1.105, 2001; \"Synchronous Optical Network (SONET) - Basic Description Including Multiplex Structure, Rates and Formats\"

[10] IEEE standard 802.3ae-2002 (Amendment to IEEE Standard 802.3-2002)

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Implementation Agreement: OIF-TFI5-0.1.0 TFI-5 TDM Fabric to Framer Interface

6. Introduction

There are a number of vendors either offering or involved in offering TDM switching fabrics. Similarly, there are a number of vendors offering TDM

framers, which interface to these switch fabrics. Traffic between the framer and the fabric is modeled after a SONET/SDH frame, and operates at the STS- 48/STM-16 equivalent bit rate over the backplane. In order to ensure device interoperability across multiple vendor devices it is important that the

electrical/optical jitter, and byte signaling protocols are compatible. This TDM Fabric to Framer Interface (TFI-5) Implementation Agreement is intended to ensure interoperability through the specification of key functions and/or parameters. The key functions specified within this document include link integrity monitoring, connection management, and mapping mechanisms for both SONET/SDH and non-SONET/SDH clients. TFI-5 is an alternative framer interface compared to SPI-5 [3], which is targeted for packet/cell switch fabrics.

At the August 2001 OIF Plenary meeting, a project was approved to

generate an Implementation Agreement called TFI-5 (TDM Fabric to Framer Interface) to connect SONET/SDH framers to TDM fabrics using I/O technologies [1] developed for SFI-5 [2] and SPI-5 [3].

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Implementation Agreement: OIF-TFI5-0.1.0 TFI-5 TDM Fabric to Framer Interface

7. Requirements

The TFI-5 interface shall have the following requirements:

• Support SONET/SDH framers with line-side interfaces of OC-48/STM-16, OC-192/STM-, and OC-768/STM-256. • Support multi-channel framers with lower rate line-side interfaces with an aggregate bandwidth of N x OC-48/STM-16. (e.g. quad OC-12/STM-4). • Support any standard compliant mix of non—concatenated, contiguously concatenated and virtually concatenated STS-1-SPE/higher order VC-3 and STS-3c-SPE/VC-4 payloads mapped within the above OC-Ns/STM-Ns. • Support G.709 OTN framers with line-side interfaces of OTU1, OTU2, and OTU3 by mapping the ODU1, ODU2 and ODU3 into SONET/SDH-like frame formats. • Support a line-side 10 GE WAN PHY interface as OC-192/STM- signal. • Support for a line-side 10GE LAN PHY interface by mapping into a SONET/SDH-like frame format. • Uses scrambling to ensure transition density.

• Support lane bandwidths of 2.488 Gbps and include a mechanism to support higher aggregate payload bandwidths across multiple lanes. All lanes are frequency locked to a common reference. Optionally, the TFI-5 link can also operate at a rate of 3.1104 Gbps (STS-60). • Support byte interleaving.

• Supports de-skew between lanes originating from multiple framers or fabric devices. De-skew algorithm must operate without additional signal lanes. • Support fabric constructed from multiple devices. • TFI-5 device shall be capable of checking for errors.

• Capable of driving at least 30 inches of PCB with 2 connectors for intra-shelf environments and at least 100 meters over optics for inter-shelf environments.

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Implementation Agreement: OIF-TFI5-0.1.0 TFI-5 TDM Fabric to Framer Interface

• Capable of bit error rate of 10E-12 for PCB and for Optical links. Will have distance de-rating for better BER. • Support DC coupling. AC coupling is optional.

• Provide a clear forward migration path to future fabrication processes. • Wide availability of components.

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Implementation Agreement: OIF-TFI5-0.1.0 TFI-5 TDM Fabric to Framer Interface

8. Interface Definition

TFI-5 is a SONET/SDH-like backplane interface, either electrical or optical, connecting a framer to a TDM switch.

A system reference model is shown in Figure 8.1. A variety of framers,

including SONET/SDH, OTN, 10GE WAN PHY and 10GE LAN PHY framers, are shown to operate simultaneously in the system. The transport of client signals through the TFI-5 system is fully specified, within the TFI-5

Implementation Agreement, for SONET and SDH signals (including the 10GE WAN PHY). The transport, through the TFI-5 system of OTN ODU1 and ODU2 clients are defined in Section 10.4. ODU3 and 10GE LAN PHY client mappings are proposed in Appendix A.

T D M S w i t c h TFI-5 Mapper TFI-5 Mapper SONET/SDHframer OTNframer OC-3/12/48/192/768STM-1/4/16//256 OTU1/2/3

SONET/SDHsignals OTN (G.709)signals

TFI-5 Mapper TFI-5 Mapper TFI-5 link

10GbE LAN PHYFramer 10GbE WAN PHY Framer 10 GbE LAN PHY

Ethernet signals

10 GbE WAN PHY(OC-192/STM-)

Figure 8.1 TFI-5 System Reference Model

As the services provided by the TFI-5 link in the Framer-to-Fabric direction, are identical to that provided in Fabric-to-Framer direction, there is only one definition of a TFI-5 link. It is applicable for either direction of traffic. Separate receive and transmit link definitions are unnecessary. All instantiations of the TFI-5 links in Figure 8.1 are identical: a 2.488 Gbps (or 3.1104 Gbps) link locked to a common system reference clock. The TFI-5 link has the following general characteristics:

1. A TFI-5 link is a point-to-point connection between a framer and a TDM switch fabric device. 2. The format of a TFI-5 link, the TFI-5 frame, is a simplification from Telcordia GR-253-CORE [4], ANSI T1.105 [9] and ITU G.707 [5]

SONET/SDH frame (see Section 10). A1/A2 bytes are used for framing, the X7 + X6 + 1 scrambling polynomial is used to ensure rich transition Optical Internetworking Forum

Implementation Agreement: OIF-TFI5-0.1.0 TFI-5 TDM Fabric to Framer Interface

density, B1 is used for link error monitoring, and B2 can be used for connection monitoring.

3. TFI-5 is defined using a layered approach. Three different layers are

defined (see Figure 10.4): Link layer, Connection layer and Mapping layer. The Link layer is generated and terminated by the TFI-5 link source and sink devices and its extent is a TFI-5 link. The Connection layer is generated/ terminated by the framer and its extent is the

connection of a tributary (an STS-1 time-slot) from the Ingress framer to the Egress framer, passing through the TDM switch fabric. The Mapping layer is also generated/terminated by the framer. It provides the

transport of client signals over one or more Connection layer time-slots. 4. All TFI-5 links are frequency locked and all theTFI-5 frames need to be relatively frame aligned within the deskew window of the fabric. Methods of aligning client signals to the TFI-5 frame include pointer processing and multiplexing/demultiplexing and/or through a mapping process. The use of TFI-5 to connect a framer to a framer, or a TDM switch to a TDM switch, is out of the scope of the TFI-5 Implementation Agreement, but is not precluded.

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Implementation Agreement: OIF-TFI5-0.1.0 TFI-5 TDM Fabric to Framer Interface

9. Signal Definition

There are only three signals defined in TFI-5; a data signal (TFIDATA), a reference clock signal (TFIREFCK) and an 8kHz frame boundary reference (TFI8KREF). TFIREFCK and TFI8KREF shall be frequency locked to each other with a relative wander of less than +/- 4 UI of TFIREFCK. TFIDATA is differential CML. Examples of intra-shelf and inter-shelf system models are provided in Figures 9.1 and 9.2. Signal Name TFIDATA

Function

The TFI-5 Data (TFIDATA) signal carries the data between the Framer and the Switch Fabric. The same signal definition is applicable to data transfer in the Framer to Fabric direction, and the Fabric to Framer direction.

Each TFIDATA link operates at 2.488 Gbps, corresponding to the standard SONET STS-48 rate and to the standard SDH STM-16 rate. Optionally, each TFIDATA link can operate at a rate of 3.1104 Gbps (STS-60), but support for the 3.1104

Gbps rate is not required. Each TFIDATA link transports TFI-5 frames (the frame format of TFIDATA). Each TFI-5 frame is modeled after a SONET / SDH stream.

TFIDATA is frequency locked to TFIREFCK.

TFIREFCK

The TFI-5 Reference Clock (TFIREFCK) signal provides timing reference to all the TFI-5 data (TFIDATA) signals in a system.

TFIREFCK is nominally a 155.52 MHz, 50% duty cycle clock. Jitter characteristics of TFIREFCK do not directly concern interoperability and are beyond the scope of this implementation agreement.

All TFIDATA signals in a system are frequency locked to TFIREFCK.

The TFI-5 8kHz Frame Reference (TFI8KREF) signal

provides reference to frame boundaries for all the devices in a TFI-5 system.

TFI8KREF is nominally a 50% duty cycle clock with a nominal frequency of 8kHz. TFIREFCK and TFI8KREF shall be

frequency locked to each other with a relative wander of less than +/- 4 UI of TFIREFCK. Table 9.1 TFI-5 Signal Summary

TFI8KREF

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Implementation Agreement: OIF-TFI5-0.1.0 TFI-5 TDM Fabric to Framer Interface TFIDATA_ITFIDATATFIDATA_OFABRICTFIDATA_OTFIREFCKTFI8KREFTFIDATAFRAMERTFIDATA_ITFIREFCKTFI8KREFSystemClock/SyncSource Figure 9.1 TFI-5 Intra-shelf system model TFIDATA_IFABRICTFIDATA_OTFIDATA_OFRAMERTFIDATA_IFRM SYNCOption 2TFIREFCKTFIREFCKTFI8KREFTFI8KREF SystemClock/SyncSourceFRM SYNC Option 1PLL Figure 9.2 TFI-5 Inter-shelf system model with two example clocking implementations. Optical Internetworking Forum 17

Implementation Agreement: OIF-TFI5-0.1.0 TFI-5 TDM Fabric to Framer Interface

10. Detailed Description

TFI-5 is a SONET/SDH-based backplane interface, either electrical or optical, connecting a framer to a TDM switch fabric. TFI-5 uses a frame-based protocol. Figure 10.1 shows the format of a generic TFI-5 frame, where parameter N is the number of STS-1 time-slots (N = 48 or 60). The colors depicting bytes in figures 10.1, 10.2, and 10.3 correspond with the layers shown in figure 10.4.

11234567

CMCMCM.....CMCMCSICSICSI.....CSICSIH1B2H1B2B2H1..........H1B2H1B2H2H2H2.....H2H2H3H3H3.....H3H3B12

.....N-3N-2N-1

A1A1NA1N+1N+2N+3N+4.....2N-12N2N+1A2A2A2..........

3N-13N3N+1

............

90N

Link layer overheadConnection layer overhead

Figure 10.1 TFI-5 Frame Format (Generic)

Figure 10.2 shows the TFI-5 2.488 Gbps frame format (N = 48). This frame has the same dimensions as a standard SONET STS-48 or SDH STM-16 frame (9 rows of 4320 columns) and shall be supported for interoperability. Figure 10.3 shows the TFI-5 3.1104 Gbps frame format (N = 60). This frame has the same dimensions as a SONET STS-60 or SDH STM-20 frame (9 rows of 00 columns). Support of the TFI-5 3.1104 Gbps rate and frame format is optional.

Optical Internetworking Forum

STS-SPE/VCarea18

Implementation Agreement: OIF-TFI5-0.1.0 TFI-5 TDM Fabric to Framer Interface

11234567

CMCMCM.....CMCMCSICSICSI.....CSICSIH1B2H1B2B2H1..........H1B2H1B2H2H2H2.....H2H2H3H3H3.....H3H3B12

.....

46A147A148A149A250A251A252

.....

.....142143144145

............

4320

Link layer overhead

Connection layer overhead

Figure 10.2 TFI-5 2.488 Gbps (STS-48) Frame Format (required support)

11234567

CMCMCM.....CMCMCSICSICSI.....CSICSIH1B2H1B2B2H1..........H1B2H1B2H2H2H2.....H2H2H3H3H3.....H3H3B12

.....

58A159A160A161A262A263A2

.....119120121122123.....178179180181

............

Link layer overhead

Connection layer overhead

Figure 10.3 TFI-5 3.1104 Gbps (STS-60) Frame Format (optional support)

There are three layers defined for TFI-5: Link, Connection and Mapping. Figure 10.4 shows the hierarchical relation between the layers.

• The TFI-5 Link layer defines the operations performed and the

information generated/terminated by the TFIDATA link source and sink devices. The TFI-5 Link layer is generated and terminated at each TFI-5 link.

Optical Internetworking Forum

STS-SPE/VCarea19

STS-SPE/VCareaImplementation Agreement: OIF-TFI5-0.1.0 TFI-5 TDM Fabric to Framer Interface

• The TFI-5 Connection layer enables monitoring of the end-to end connection of each STS-1 time-slot from Ingress framer to Egress framer, passing through the TDM switch fabric. • The TFI-5 Mapping layer performs the association and mapping of

client signals to one or more STS-1 time-slots of the Connection layer. In order to carry client signals with bandwidths greater than that of a single TFI-5 link, the TFI-5 Mapping Layer can group a set of STS-1 time-slots transported in different TFI-5 links (inverse multiplexing). Figure 10.5 shows the extent of each TFI-5 layer using a simplified STS-1 cross-connect model. This simplified model separates the Ingress framers (receivers) and the Egress framers (transmitters) in order to simplify the description.

Client signal

Mapping LayerConnection LayerLink LayerTFI-5 Link

Figure 10.4 TFI-5 Layers

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Implementation Agreement: OIF-TFI5-0.1.0 TFI-5 TDM Fabric to Framer Interface

TFI-5 Mapping LayerTFI-5 Connection LayerTFI-5 Link LayerIngress Framer #1.....Mappingof clientsignalsSTS-1 (x48)connect.monitoringSTS-1 (x48)connect.monitoringSTS-1 (x48)connect.monitoringSTS-1 (x48)connect.monitoringLinkframerLinkframerLinkframerLinkframerTFI-5 Link LayerTFI-5 LinkSwitchLinkframerLinkframerLinkframerLinkframerLinkframerLinkframerLinkframerLinkframerTFI-5 LinkEgress Framer #1LinkframerLinkframerLinkframerLinkframerSTS-1 (x48)connect.monitoringSTS-1 (x48)connect.monitoringSTS-1 (x48)connect.monitoringSTS-1 (x48)connect.monitoringMappingof clientsignals.....STS-1Time SlotInterchangeIngress Framer #n.....Egress Framer #n...............

Figure 10.5 TFI-5 Layers Example (an STS-1 cross-connect)

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Implementation Agreement: OIF-TFI5-0.1.0 TFI-5 TDM Fabric to Framer Interface

10.1 TFI-5 Link Layer

The Link layer is generated and terminated at each TFI-5 link. The Link layer is independent of the client payload that forms the data stream multiplexed across a group of TFI-5 links. The Link layer embodies the electrical

signaling and link rate specifications, link framing, link scrambling, link error monitoring and frame deskew functions. The Link layer operates on each link independently.

The Period of transmission of a TFI-5 frame is 125 µs. Two different baud rates are defined: the standard SONET/SDH 2.488 Gbps transmission rate and an optional 3.1104 Gbps transmission rate. Support of the 3.1104 Gbps transmission rate is not required.

The TFI-5 2.488 Gbps frame format is shown in Figure 10.2. The TFI-5 frame format for the optional rate 3.1104 Gbps is shown in Figure 10.3. The bytes and bits are transmitted as defined in [14, 15, 24]: the order of transmission of the TFI-5 frame bytes (Figures 10.2 and 10.3) is first from left to right and then from top to bottom. Within each byte the most significant bit is transmitted first.

The overhead bytes A1, A2 and B1 as shown in figure 10.1, 10.2 and 10.3 are used by the Link layer for frame delineation and supervision purposes. These bytes are generated by each TFI-5 link transmitter (TFI-5 link source device) and terminated by each TFI-5 link receiver (TFI-5 link sink device).

10.1.1 TFI-5 Frame Delineation (A1A2 bytes)

The TFI-5 frame shall contain three A1/A2 pairs (three A1 bytes followed by three A2 bytes) located in the first row. The three A1 bytes are located in columns N-2, N-1 and N, and the three A2 bytes are located in columns N+1, N+2 and N+3 (N = 48, 60). The source device of a TFI-5 link shall insert this 6-byte sequence. The A1 bytes carry the value 0xF6 and the A2 bytes carry the value 0x28.

The sink device of the TFI-5 link locates the TFI-5 frame boundaries by

searching for the framing pattern contained In the A1 and A2 bytes as defined above. Implementations of TFI-5 framers may frame on a subset of the 3 A1 and 3 A2 bytes.

Upon startup or reset the sink device goes to the OOF (Out Of Frame) state (Figure 10.5.1). The sink device shall transition from the OOF state to the INF (In-Frame) state after finding the framing pattern, one TFI-5 frame apart (125 µs), for M1 consecutive frame times. M1 is defined to be 2 frames in this

standard. Once in the INF state, the sink device shall continue to monitor for correct alignment. The sink device of the TFI-5 link shall transition from the INF state to the OOF state if the framing pattern is not found (at least one

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Implementation Agreement: OIF-TFI5-0.1.0 TFI-5 TDM Fabric to Framer Interface

incorrect bit) during M2 consecutive frames. M2 is defined to be less than or equal to 5 frames in this standard.

ResetM1 consecutive framingpattern matchesLess then M1consecutive “good”Framing patternsOOFIn FrameLess then M2consecutive “bad”Framing patterns

Figure 10.5.1 TFI-5 State Diagram for Out of Frame and In Frame Conditions

When the sink device of a TFI-5 link is in the OOF state it shall alert the downstream element by overwriting to “all ones” all of the bytes in the Connection and Mapping Layers.

10.1.2 TFI-5 Frame Scrambling

TFI-5 links are scrambled to ensure rich transition density. The TFI-5 link is scrambled with the SONET/SDH polynomial of X7 + X6 + 1. The scrambling is done in the same way as for a standard SONET/SDH frame, as per [14, 15, 24]:

• The residue of the scrambler is initialized to all ones on the most-significant bit of the byte in row 1 and column [3*N]+1 (N = 48, 60) of the TFI-5 frame: this is the first SPE byte of a SONET/SDH frame • The scrambler is disabled for the bytes located in columns 1 to 3*N (N = 48, 60) of the first row: this is the whole first SOH row of a SONET/SDH frame. As an option, it is possible to enable the scrambling of the bytes in columns 1 to N-3 and N+4 to 3*N (N = 48, 60) of the first row. The bytes in columns N-2 to N+3 (N = 48, 60) are never scrambled, but the scrambler shall continue to run during these byte positions. When this option is enabled, columns 1 to N-3 and N+4 to 3*N (N = 48, 60) of the first row of the current TFI-5 frame are scrambled with the scrambler running from the reset in the previous TFI-5 frame. This optional “STS-768-like” scrambling mode can be used to assure an adequate number of transitions when the positions in columns 1 to N-3 and N+4 to 3*N of the first row of the TFI-5 frame are used by the Mapping layer.

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M2 consecutive mismatched

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Implementation Agreement: OIF-TFI5-0.1.0 TFI-5 TDM Fabric to Framer Interface

When bytes 1 to N-3 and bytes N+4 to 3N are used by the Mapping layer, and the standard SONET/SDH mode of scrambling is enabled, the content of these bytes must be compliant with ITU-T G.957 Appendix II: Consecutive Identical Digits (CID).

Scrambling by all devices in a TFI-5 system should utilize the standard SONET scrambling unless all devices on the link support the optional

scrambling mode. For applications that use bytes 1 to N-3 and bytes N+4 to 3N as Mapping layer bytes where sufficient transition density cannot be ensured, it is a requirement to support the STS-768-like scrambling mode.

10.1.3 TFI-5 Link Error Monitoring (B1 byte)

TFI-5 links can be monitored using bit-interleaved (BIP-8) parity for

transmission errors. The definition of the B1 byte is lifted directly from [14, 15, 24]. The B1 byte is located in the first column of the second row of the TFI-5 frame (see Figure 10.1) and carries a BIP-8 code using even parity. The BIP-8 is calculated over all the bytes in the previous TFI-5 frame after scrambling and is placed in the B1 byte of the current frame before scrambling.

In order to allow fault isolation the BIP-8 shall be calculated and inserted in the B1 byte by the source device of every TFI-5 link. The sink device of every TFI-5 link shall monitor the B1 byte.

10.1.4 TFI-5 Link Deskew

All TFI-5 links in a system have a 2.488 Gbps standard rate (or optionally a 3.1104 Gbps rate) and are frequency locked to a common clock reference (TFIREFCK). In order to be able to properly time-slot exchange different client payloads from multiple TFI-5 links across the fabric interfaces, the frame boundaries of the source links shall be closely aligned.

The start of a TFI-5 frame has a relative offset from the rising edge of

TFI8KREF of (T) TFIREFCK cycles. T shall have a range of 1 full TFI8KREF cycle, and settable in increments of 8 TFIREFCK cycles or finer. The framer shall output the first A2 byte (byte N+1)of the frame at offset (T) with a timing accuracy of +/- 8 TFIREFCK cycles. Programmable offset (T) only applies to framers. The accuracy applies to both TFI-5 framers and switch fabrics.

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Implementation Agreement: OIF-TFI5-0.1.0 TFI-5 TDM Fabric to Framer Interface

TFI8KREF

TFI Frame_aTFI Frame_b

-8 TFIREFCK+ 8 TFIREFCKProgrammable offsetvalue (T)

Figure 10.5.2 TFI-5 frame offset timing

When a set of TFI links contains client payloads that are to be switched or multiplexed together, the sink device receiving these links shall be able to tolerate total (skew + relative_wander/2) of at least 48 bytes. The arrival time between the earliest and latest arriving functional links at the sink device shall be less than 48 bytes.

Methods of achieving the standard TFI-5 alignment include pointer processing (retiming), multiplexing/inverse-multiplexing and mapping.

10.2 TFI-5 Connection Layer

The TFI-5 Connection layer is defined for each of the N STS-1 time-slots (N = 48, 60) transported inside a TFI-5 frame. The Connection layer extends end-to-end from the ingress framer to the egress framer. Optionally it provides for the following services for each STS-1 time-slot: supervision of errors and supervision of connectivity. The TFI-5 Connection layer uses the B2 and CM (Connection Monitoring) bytes as shown in Figures 10.1, 10.2 and 10.3 for these purposes.

10.2.1 TFI-5 Connection Error Monitoring (B2 byte)

Connection error monitoring is optional. The N B2 bytes (see Figure 10.1) are carried in columns 1 to N (N = 48, 60) of the fifth row of the TFI-5 frame (see Figure 10.1). These are the same positions as the B2 bytes in a

standard SONET/SDH frame. One B2 byte is allocated in each STS-1 time-slot for a Connection layer bit-error monitoring function. Each B2 byte is a Bit Optical Internetworking Forum

Implementation Agreement: OIF-TFI5-0.1.0 TFI-5 TDM Fabric to Framer Interface

Interleaved Parity 8 code (BIP-8) using even parity. Each BIP-8 code is computed over all bits of the previous frame of the STS-1 time-slot (before Link layer scrambling) except the associated STS-1 time-slot bytes located in columns 1 to 3*N (N=48,60) of the first three rows of the TFI-5 frame. This BIP-8 code is placed in the B2 position of the current STS-1 time-slot. This is the same definition as for the standard SONET/SDH B2 bytes, where B2 is calculated over all bits of the Line OH and the Envelope Capacity of the previous STS-1 time-slot. If connection error monitoring is not used the B2 byte positions can be used by the TFI-5 Mapping layer. When connection error monitoring is implemented, a TFI-5 compliant device supporting this option shall provide means to disable B2 insertion at the source and B2 monitoring at the sink.

10.2.2 TFI-5 Connection Connectivity Monitoring (CM byte)

Connection connectivity monitoring is optional. The N CM bytes (see Figure 10.1) are carried in columns N+1 to 2*N of the ninth row of the TFI-5 frame (N = 48, 60). These are the same positions as the M0/M1/Z2 bytes in a standard SONET/SDH frame. The CM format is shown in Figure 10.6. The CM bytes allow the monitoring of each constituent STS-1 time-slot for switch misconnections.

msb

lsb

User Message (7 bits)CID [20:14] (7 bits)CID [13:7] (7 bits)CID [6:0] (7 bits)Frame 1Frame 2Frame 3Frame 4

1000

Figure 10.6 TFI-5 Connection Monitoring (CM) multi-frame format The CM multi-frame spans four TFI-5 frames and carries a 7-bit User Message field and a 21-bit Connection Identifier (CID). Setting the most

significant bit of the CM byte high shall identify the first frame in the CM multi-frame. The most significant bit of the CM bytes of the 3 remaining frames shall be set low.

When CM is implemented, the CID field shall be configurable by system

software at the TFI-5 source device and shall be readable by system software at the sink device to uniquely identify every constituent STS-1 time-slot within every TFI-5 link within a system.

When CM is implemented, the TFI-5 sink process shall be able to monitor the CID field by comparing its value to the value of the expected CID in order to detect misconnections at the switch fabric. Persistence shall be used to prevent bit errors from causing connection management mismatches.

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If connection connectivity monitoring is not used the CM byte positions can be used by the TFI-5 Mapping layer. When connection connectivity monitoring is implemented, a TFI-5 compliant device supporting this option shall provide means to disable CM insertion at the source and CM monitoring at the sink.

10.2.3 TFI-5 Connection forward defect indication

In case of a TFI-5 link failure (Loss of signal, out of frame) the down stream signal (connection and mapping layer) is set to “all ones”. This condition can be detected by a “1111 1111” code in the CSI bytes if CSI is supported. The generation of client signal specific forward defect indications (e.g.

SONET/SDH AIS, ODU-FDI) has to be done in the egress framer and is outside the scope of the TFI-5 specification. 10.2.4 TFI-5 Connection open indication

If an STS-1 time-slot at the output of the TDM switch fabric is not connected to any input STS-1 time-slot all Connection and Mapping layer bytes of this time-slot shall be set to zero. This condition can be detected by a “0000 0000” code in the CM bytes if CM is supported. The generation of the client signal specific unequipped or open connection signal (e.g. STS-SPE/VC

Unequipped, ODU Open Connection Indication) has to be done on the egress framer and is outside the scope of the TFI-5 specification.

10.3 TFI-5 Mapping Layer

The TFI-5 Mapping layer provides the transport of the client signals over one or more TFI-5 Connection layer time-slots. All the bytes of the TFI-5 frame that are not used by the Link and Connection layer are available for the Mapping layer (see Table 10.1).

If bytes of the TFI-5 frame are not used by the Mapping, Connection or Link layer they shall be undefined except for the bytes 1 to N-3 in row 1 which shall be set to 0xF6 and the byte N+4 to 2*N in row 1 which shall be set to 0x28.

The basic mapping scheme uses the SONET/SDH structure as defined in [14,15,24].

Non-SONET/SDH client signals can be transported across the TFI-5 by mapping them inside a concatenated group of SONET/SDH STS-3c SPEs/VC-4s. As all the TFI-5 signals are frame aligned and the payload frames are also aligned to a fixed pointer offset, no specific overhead for alignment is required within TFI-5 for transporting non-SONET/SDH clients.

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Implementation Agreement: OIF-TFI5-0.1.0 TFI-5 TDM Fabric to Framer Interface

Type Name Positions Bytes that belong to the Link Layer

A1 A2 B1

Bytes that are optionally

used by the Connection layer otherwise they may be used by the Mapping Layer

B2 CM

Columns N-2 to N of the 1st row Columns N+1 to N+3 of the 1st row Column 1 of the 2nd row Columns 1 to N of the 5th row Columns N+1 to 2*N of the 9th row

Bytes that are optionally used for Client Status Indication otherwise they may be used for other Mapping Layer functions Bytes that are optionally used by the Mapping layer otherwise they default to 0xF6, 0x28, respectively Bytes that belong to the Mapping layer for payload transport

CSI

Columns 2N+1 to 3*N of the 9th row

- -

Columns 1 to N-3 of the 1st row Columns N=4 to 2*N of the 1st row

All other

Table 10.1 Layer Assignments of TFI-5 bytes

TFI-5 Client Status Indication (CSI byte)

Client Status Indication is optional. The Client Status Indication (CSI) bytes provide a mechanism for the framer to report the status of client signals and/or to send commands to the switch fabric. This information can be used to control protection switching on the switch fabric. The encoding of CSI is unique for each client type as the alarms and conditions are dissimilar. Client Status Indication (CSI) is provided in a single byte (E2 byte in

SONET/SDH) for each STS-1. The CSI bytes (see Figure 10.1) are carried in columns 2*N+1 to 3*N of the ninth row of the TFI-5 frame (N = 48, 60). The CSI byte shall be provisioned to the E2 SONET/SDH Transport Overhead (TOH) byte. Tables 10.2 and 10.3 show the relevant byte assignments: The following rules apply to the generation and interpretation of CSI when it is implemented:

1. CSI codes are assigned in order of alarm/condition priority. (High priority alarm/conditions have high CSI code values).

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2. The framer sets the CSI codes in all time-slots associated with each client to the same value

10.3.1 Mapping of SONET/SDH client signals

As a default SONET/SDH STS-1-SPE, STS-3c-SPE, STS-Nc-SPE, VC-4, VC-4Xc and higher order VC-3 are mapped into TFI-5 time-slots. For certain applications the transport of SONET/SDH TOH/SOH over the TFI-5 system can be supported.

10.3.1.1 Mapping of SONET/SDH STS-SPEs/higher order VCs clients

SONET/SDH STS-SPEs/higher order VCs clients are transported in a TFI-5 signal in the same way as they are transported in a STS-N/STM-N signal (see [14,15, 24]). An STS/AU structure, as defined in [5], is aligned to the TFI-5 frame, is constructed with the STS-SPE/higher order VC and pointer. (In this section, the term “STS/AU structure” is equivalent to SDH AU structure.) If the client is not already aligned to the TFI-5 frame or differs from the TFI-5 bit rate, pointer justification is required.

Note: SONET does not define a structure that is the equivalent to the SDH AU structure. In SONET terms the AU structure consists of the STS envelope capacity and the related H1, H2 and H3 pointer bytes in the TOH.

The STS/AU structure is mapped into the H1, H2, H3 pointer bytes and STS-SPE/VC payload area of the TFI-5 frame (see Figure 10.1). An STS-1/AU-3 is mapped into a single TFI-5 time-slot. 󰂃 An STS-3c/AU-4 is mapped into 3 TFI-5 time-slots.

󰂃 Contiguous concatenated STS-3*Nc/AU-4-Nc signals are mapped into

3*N time-slots of a TFI-5 frame. 󰂃 A STS/AU structure that exceeds the capacity of a single TFI-5 signal is mapped to time-slots in several TFI-5 signals (disinter leaving).

Figure 10.7 shows an example of mapping a STS-768 client onto a set of 16 TFI-5 links. After alignment to the TFI-5 frame, client bytes are taken in sets of 16 and placed onto TFI-5 links. Namely, bytes 1-16 are placed on TFI-5 link #1, bytes 17-32 on TFI-5 link #2, and bytes 241-256 on TFI-5 link #16. Figure 10.8 shows an example of mapping an STS-192/STM- client into a set of 4 TFI-5 links. After alignment to the TFI-5 frame, client bytes are taken in sets of 16 and placed onto TFI-5 links. Namely, bytes 1-16 are placed on link #1, bytes 17-32 are placed on link #2, and bytes 49- are placed on link #4. See ITU-T G.707.

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󰂃 A STS/AU structure can use time-slots in different TFI-5 signals even if the structure doesn’t exceed the capacity of a TFI-5 signal. TFI-5 requires neither special processing nor overhead to carry virtually concatenated clients.

󰂃 Virtual concatenated signals are treated as individual STS-SPE/VC signals. 󰂃 A TFI-5 system supports any standard mixture of non-concatenated, contiguous and virtually concatenated signals. 󰂃 The STS-SPE/VC transported in a TFI-5 signal can come from several OC-N/STM-N signals (e.g. 4 OC-12 interfaces are supported by a TFI-5). 󰂃 The time-slot assignment in the TFI-5 signal may follow the time-slot assignment in the OC-N/STM-N interface signal. This assignment is not followed, for example, for framers with time-slot interchange.

1Order16 reserved1234567bytes1 B115 reserved...........4416 reservedbytes4516 A1bytes4616 A1bytes4716 A1bytes4816 A1bytes4916 A2bytes5016 A2bytes5116 A2bytes5216 A2bytes5316 reservedbytes...........9616 reservedbytes971 J015 Z0......Link 1Link 2Link 3Link 4Link 5Link 6Link 7Link 8Link 9Link 10Link 11Link 12Link 13Link 14Link 15Link 1616 reserved bytes16 reserved bytes16 reserved bytes16 reserved bytes16 reserved bytes16 reserved bytes16 reserved bytes16 reserved bytes16 reserved bytes16 reserved bytes16 reserved bytes16 reserved bytes16 reserved bytes16 reserved bytes16 reserved bytes16 reserved bytes16 reserved bytes16 reserved bytes16 reserved bytes16 reserved bytes16 reserved bytes16 reserved bytes16 reserved bytes16 reserved bytes16 reserved bytes16 reserved bytes16 reserved bytes16 reserved bytes16 reserved bytes16 reserved bytes16 reserved bytes16 reserved bytes16 reserved bytes16 reserved bytes16 reserved bytes16 reserved bytes16 reserved bytes16 reserved bytes16 reserved bytes16 reserved bytes16 reserved bytes16 reserved bytes16 reserved bytes16 reserved bytes16 A1 bytes16 A1 bytes16 A1 bytes16 A1 bytes16 A2 bytes16 A2 bytes16 A2 bytes16 A2 bytes16 reserved bytes16 reserved bytes16 reserved bytes16 reserved bytes16 reserved bytes16 reserved bytes16 reserved bytes16 reserved bytes16 reserved bytes16 reserved bytes16 reserved bytes16 reserved bytes16 reserved bytes16 reserved bytes16 reserved bytes16 reserved bytes16 reserved bytes16 reserved bytes16 reserved bytes16 reserved bytes16 reserved bytes16 reserved bytes16 reserved bytes16 reserved bytes16 reserved bytes16 reserved bytes16 reserved bytes16 reserved bytes16 reserved bytes16 reserved bytes16 reserved bytes16 reserved bytes16 reserved bytes16 reserved bytes16 reserved bytes16 reserved bytes16 reserved bytes16 reserved bytes16 reserved bytes16 reserved bytes16 reserved bytes16 reserved bytes16 reserved bytes16 reserved bytesJ0Figure 10.7 Example disinterleaving showing byte ordering of an STS-768

frame into 16 TFI-5 links

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Order123416 A1Bytes1 B115 Res16 A116 A116 A116 A116 A216 A216 A216 A2BytesBytesBytesBytesBytesBytesBytesBytes16 A21 J0Bytes15 Z09Link 1Link 2Link 3Link 416 A1 Bytes16 A1 Bytes16 A1 Bytes16 A2 Bytes16 A2 Bytes16 A2 Bytes16 A1 Bytes16 A1 Bytes16 A1 Bytes16 A2 Bytes16 A2 Bytes16 A2 Bytes16 A1 Bytes16 A1 Bytes16 A1 Bytes16 A2 Bytes16 A2 Bytes16 A2 Bytes16 A1 Bytes16 A1 Bytes16 A1 Bytes16 A2 Bytes16 A2 Bytes16 A2 BytesJ0 Figure 10.8 Example of disinterleaving showing byte ordering of an STS-192 frame into 4 TFI-5 links 10.3.1.2 TOH/SOH bytes

SONET section/line overhead (TOH), SDH regenerator/multiplex section overhead (SOH) and AU pointer bytes may be transported via a TFI-5 frame using the bytes 1 to 3*N in row 1 to 3 and 5 to 9 that are not used by the Link or Connection layers.

󰂃 The TOH/SOH bytes may be assigned to the same positions as in a

standard SONET/SDH frame or use different positions (e.g. if the position is used by TFI-5). This is transparent to the TFI-5 signal and outside the scope of this implementation agreement. 󰂃 TOH/SOH bytes from a OC-N/STM-N signal may be distributed over

several TFI-5 signals. 󰂃 A TFI-5 signal may transport TOH/SOH bytes from several OC-N/STM-N interfaces. 󰂃 Alignment of the TOH/SOH bytes to the TFI-5 clock is normally

required. This alignment process is not standardized and outside the scope of the TFI-5 specification. Note that the bytes in column 1 to 3*N belong to specific STS-1 time-slots of the TFI-5 Connection layer and take the same route as these time-slots in a TFI-5 system.

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10.3.1.3 CSI coding for SONET/SDH clients

SONET/SDH status are encoded into the CSI byte as shown in Table 10.2 below.

CSI Code 1111 1111 1111 1111 1111 1110 1111 1101 1111 1100

Alarm/Condition TFI-5 Link Loss of Signal TFI-5 Link Loss of Frame Software Force - Away Software AIS Insert Software Force-To Loss of Signal (LOS) Loss of Frame (LOF)

Section Trace Identifier Mismatch (TIM-S)

Line AIS (AIS-L)

Signal Fail (SF-L) / Excessive BER (EXC-MS) Path AIS (AIS-P) / Concat AIS (AISC-P)

Loss of Pointer (LOP) / Loss of Concat Ind (LOPC) Unequipped Signal Label (UNEQ) Path Trace Identifier Mismatch (TIM-P) Payload Label Mismatch (PLM)

Signal Fail (SF-P) / Excessive BER (EXC-P) PDI-P code 28 PDI-P code 27

…

0000 0001 0000 0000

PDI-P code 1

Signal Degrade (SD-P) Signal Degrade (SD-L) No Alarm Reserved

Table 10.2 Client Status Indication (CSI) Coding for SONET/SDH clients •

The blank CSI code values are user programmable.

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• Above each alarm/condition with a blank code point, there may be a user defined CSI alarm/condition entry. These may be used for augmenting the listed alarms/conditions with other simultaneously occurring alarms/conditions (e.g. Path alarm with SD-L).

• Generation of the CSI byte for alarms/conditions with blank code points are application dependent.

10.3.2 Mapping of OTN clients

The ODU1, ODU2 and ODU3 signals of the OTN (see [6]) are supported by a TFI-5 system. ITU-T defines the use of Virtual Concatenation for the

transport of an OTN entity over SDH paths. Diverse routing of the VC-4-Xv’s (X=17,68) requires large deskew buffers and H4 byte processing. Within the TFI-5 system, however, the differential delay between the different VC-4’s (members of a group) is limited to 48 bytes. Therefore, the transport of an ODUk through a TFI-5 system does not require the implementation of any virtual concatenation mechanisms such as differential delay compensation and H4 processing as defined in [14,15, 24].Table 10.3 shows the C-4-Xc structure used for mapping and the number of STS-3c/VC-4’s time-slots required for transport of the different ODUk signals within the TFI-5 system.

# STS-3c/VC-4’s time-slots required for transport within TFI-5 system

17 68 272

Client Signal Nominal Bit Rate (Mb/Sec) ITU-T Mapping

ODU1 2498.775126 C-4-17c ODU2 10037.273924 C-4-68c ODU3 40319.2183 C-4-272c Table 10.3 Transport of OTN entities over TFI-5 link(s) via STS-3c/VC-4 Time-slots

10.3.2.1 Mapping of a ODU1 client signal

The transport of a ODU1 client signal across a TFI-5 shall be done by

mapping the ODU1 into a C-4-17c as defined in [7] and by transporting this concatenated container over 17 STS-3c-SPE/VC-4. The active offset of the VC-4 shall be 522 (pointer offset value) for ODU1 mappings.

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Figure 10.4.2 details how the C-4-17c structure carrying an ODU1 after being mapped is transported through a TFI-5 system using 17 STS-3c/VC-4 time-slots: the C-4-17c concatenated structure is column disinterleaved over the 17 STS-3c/VC-4 time-slots. The 17 VC-4’s generated in this way are aligned to the pointer value of 522 and then transported over any combination of TFI-5 links. The first column of the STS-3c/VC-4 time-slots (equivalent bytes J1, B3, C2, etc… in a SONET/SDH frame) are unused (see Figure 10.4.2) and have undefined value. The STS-3c/VC-4 time-slots can be striped over multiple TFI-5 links, or multiplexed and carried over 1 or more links. See Section 10.2.2 for information on the Connectivity Monitoring (CM byte).

C-4-17c

RRRRRR.............................................2

1718

.............................................JJJJJJJJJ..........................................................

4404...4420

COLUMNDISINTERLEAVING

RR9R1525355

J1B31J1B3C2G1F2C2G1F2H4F3K3N1Figure 10.4.2: Disinterleaving of a C-4-17c for transport over TFI-5 link(s)

using 17 STS-3c/VC-4 time-slots Figure 10.4.3 details the reconstruction of the C-4-17c from the 17 STS-3c/VC-4 time-slots (received from any combination of TFI-5 links). The 17 STS-3c/VC-4 time-slots, are column interleaved to obtain the C-4-17c.

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.....9

H4F3K3N1VC-4 # 17VC-4 # 1123261

Implementation Agreement: OIF-TFI5-0.1.0 TFI-5 TDM Fabric to Framer Interface

J1B3261

1J1B3C2C2G1F2H4F3K3N1.....9

COLUMNINTERLEAVING

G1F2H4F3K3N1VC-4 # 17VC-4 # 111RRRRRRRR23.............................................1718.............................................525355JJJJJJJJJ.............................................9RC-4-17c4404...4420Figure 10.4.4: Interleaving of a C-4-17c from 17 STS-3c/VC-4 time-slots 10.3.2.2 Mapping of a ODU2 client signal

The transport of a ODU2 client signal across a TFI-5 shall be done by

mapping the ODU2 into a C-4-68c as defined in [7] and by transporting this concatenated container over 68 STS-3c-SPE/VC-4. The active offset of the VC-4 shall be 522 (pointer offset value) for ODU2 mappings.

Figure 10.4.5 details how the C-4-68c structure carrying an ODU2 after being mapped is transported through a TFI-5 system using 68 STS-3c/VC-4 time-slots: the C-4-68c concatenated structure is column disinterleaved over the 68 STS-3c/VC-4 time-slots. The 68 STS-3c/VC-4’s generated in this way are aligned to the pointer value of 522 and then transported over any combination of TFI-5 links. Columns 3N+N (N=48,60) of the TFI-5 frame (Equivalent bytes J1, B3, C2, etc… in a SONET/SDH frame) are unused (see Figure 10.1) and have undefined value. The STS-3c/VC-4 time-slots can be striped over

multiple TFI-5 links, or multiplexed and carried over 4 or more links. For OTN client mappings, the POH overhead bytes are undefined. See Section 10.2.2 for information on the Connectivity Monitoring (CM byte).

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C-4-68c1

RRRRRR.............................................2

RRRRRRRRR..........................................................

17613...17680

COLUMNDISINTERLEAVING

RR9R1....68697071....136

J1B31J1B3C2G1F2C2G1F2H4F3K3N1Figure 10.4.5: Disinterleaving of a C-4-68c for transport over TFI-5 link(s)

using STS-3c/VC-4 time-slots

Figure 10.4.6 details the reconstruction of the C-4-68c from the 68 STS-3c/VC-4 time-slots (received from any combination of TFI-5 links). The 68 STS-3c/VC-4 time-slots, are column interleaved to obtain the C-4-68c.

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J1B3261

1J1B3C2C2G1F2H4F3K3N1.....9

COLUMNINTERLEAVING

G1F2H4F3K3N1VC-4 # 68VC-4 # 111RRRRRRRR23...68.............................................697071RRRRRRRRR136.............................................9RC-4-68c17613...17680Figure 10.4.6: Interleaving of a C-4-68c from 68 STS-3c/VC-4 time-slots

10.3.2.3 Mapping of a ODU3 client signal

The transport of a ODU3 client signal across a TFI-5 shall be done by

mapping the ODU3 into a C-4-Xc (a possible mapping is given in Appendix A.1) and by transporting this concatenated container over n STS-3c-SPE/VC-4. The active offset of the VC-4 shall be 522 (pointer offset value) for ODU3 mappings.

10.3.2.4 CSI Coding for OTN clients

OTN status is encoded into the CSI byte as shown in Table 10.4 below.

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CSI Code 1111 1111 1111 1111 1111 1110 1111 1101 1111 1100

Alarm/Condition TFI-5 Link Loss of Signal TFI-5 Link Loss of Frame Software Force - Away Software AIS Insert Software Force-To Loss of Signal (LOS)

OTUk AIS (AIS-OTUk)

Loss of Frame (LOF) Loss of Multi-Frame (LOM)

OTUk Trail Trace Identifier Mismatch

(TIM-OTUk)

OTUk Signal Fail / Excessive BER (SF-OTUk)

ODU Open Connection Indication (OCI-ODUk)

ODUk Locked Defect (LCK-ODUk)

ODUk AIS (AIS-ODUk)

0000 0001 0000 0000

ODUk Trail Trace Identifier Mismatch

(TIM-ODUk)

ODUk Signal Fail / Excessive BER (SF-ODUk)

ODUk Signal Degrade (SD-ODUk) OTUk Signal Degrade (SD-ODUk) No Alarm Reserved

Table 10.4: Client Status Indication (CSI) Coding for OTN clients. •

The blank CSI code values are user programmable.

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• Generation of the CSI byte for alarms/conditions with blank code points are application dependent.

10.3.3 Mapping of Ethernet clients

10 GE signals as defined in [8] are supported by a TFI-5 system.

10.3.3.1 Mapping of 10 GbE LAN PHY

The transport of a 10 GbE LAN PHY client signal across a TFI-5 shall be done by mapping the 10 GbE LAN PHY into a C-4-Xc (a possible mapping is given in Appendix A.2) and by transporting this concatenated container over n STS-3c-SPE/VC-4. The active offset of the VC-4 shall be 522 (pointer offset value) for 10GE LAN PHY mappings. For 10 GbE LAN PHY mappings, the POH overhead bytes are undefined. 10.3.3.2 Mapping of 10 GbE WAN PHY

The 10 GbE WAN PHY is based on a OC-192/STM- signal with a STS-192c-SPE/VC-4-c. It is treated like standard SONET/SDH signals in a TFI-5 system.

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11. Electrical Interface Definition

This section describes the signaling that allows for TFI-5 link operation at 2.488 Gbps to 3.11 Gbps. The specification defines the characteristics

required to communicate between an TFI-5 driver and an TFI-5 receiver using copper signal traces across a communication backplane consisting of

approximately 30 inches (76 cm) of total PCB trace including two connectors. The characteristic impedance of the signal traces is nominally 100 ohms differential. Connections are point-to-point and signaling is unidirectional. TFI-5 devices from different manufacturers shall be inter-operable.

SerDes

Electrical Channel30\" FR4 + 2 connectors

SerDes

ClockSourceClockSource

TP1TP4Figure 11.1 TFI-5 application model for the pure electrical interface, also

called the intra-rack system.

Differential signaling conventions are shown in Figure 11.2 below. The differential amplitude represents the value of the voltage between the true and complement signals. Peak-Peak voltage is defined as 2*(Vhigh – Vlow). The common mode voltage is the average of Vhigh and Vlow.

Figure 11.2 General Signal Definition

TrueVhighVCMComplementVlow

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11.1 Differential Output Characteristics

Output parameters that can be derived from other specified parameters may not be explicitly specified. The use of external DC blocking capacitors is

optional. Any loss or jitter caused by these capacitors must be accounted for as part of the allocation for the printed circuit board on which the capacitors reside.

The frequency dependent attenuation of the inter-connection media degrades the signal and thus produces inter-symbol interference or data dependent jitter. Given this and the receiver eye mask, transmit emphasis shall be required.

All TFI-5 output drivers shall meet all the parameters of Table 11.1. The

receiver eye mask is provided in Figure 11.6 and Table 11.3 and assumes the TFI-5 channel model (See the Channel Model Section below). This allows maximum design flexibility while still guaranteeing interoperability.

Transmitter interoperability shall be tested using the methodology described in the OIF CEI IA section 2.2.3

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Symbol Parameter Max Min Units Comments Vod Output 1.4 Vppd Min is implied given channel and

Differential receiver eye mask Voltage

Voh Output High 2.3 V AC coupled. If DC coupled parameter

Voltage can be calculated from Vod and Vcm.

Vol Output Low -0.1 V AC coupled. If DC coupled parameter

Voltage can be calculated given Vod and Vcm.

VCM Output Common Vtt 0.62 V (Vhigh + Vlow) / 2. When using a load of

Mode Voltage Figure 11.3 with 1.05VRD <125 ohms, 0TDRF Driver Rise/Fall 50 ps At 20% - 80% into 100 ohm load

Time

IDSHORT Short 70 -70 mA Resulting DC current from a forced

Circuit Current voltage when the Tx is powered on or

off. See note 2 and Figure 11.5.

UID Unit Interval 402 321 ps 2.488 Gbps to 3.11 Gbps,

±100 ppm

RSE Single-ended 62.5 37.5 Ohm at DC

output impedance RD Differential 125 75 Ohm at DC

Impedance

RLSE Single-ended 7.5 dB From 0.004*baud rate to 0.75*baud

return loss rate

RLOUT Differential return 7.5 dB From 0.004*baud rate to 0.75*baud

loss rate

Table 11.1: TFI-5 Output Characteristics

Notes 1. The Vtt values take into account a maximum of +/-50mv ground shift between transmit and

receiver. If higher values in ground shift are within the system, then AC coupling should be used.

2. Current after 10µS to any voltage between –0.05 and 1.45V if DC coupling allowed or

required, or between –0.05 and 2.35V if AC coupling allowed or required. The time 0µS is defined as the instant when the applied voltage is turned on. dV/dT changes within this range are to be below 1V/µS. See Figure 11.5 for more info.

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11.2 Differential Input Characteristics

All TFI-5 input receivers shall meet all the parameters of Table 11.2,

Figure 11.3 and Figure 11.5. Also the receive eye mask of Table 11.3 and Figure 11.6 must be met.

Symbol Parameter Max Min Units Comments Vtt Termination 1.30 1.10 V Parameter unspecified if DC blocking

Voltage capacitors are present

ZVtt Bias Voltage 30 Ohm From DC to .75*baud rate if DC

Source blocking capacitors are not present. Impedance From 500Mhz to .75*baud rate if DC

blocking capacitors are present. (see note 1)

VRCM Input Common Vtt 0.6 V (Vhigh + Vlow) / 2, (see note 2)

Mode Voltage Parameter unspecified if DC blocking

capacitors are present

ZINDIFF Differential 125 75 Ohm At DC as in Figure 11.3. If AC coupled,

input parameter applies at 0.0035*Fd only impedance

RLIN Differential 10 dB From 0.004*baud rate to 0.75*baud rate

return loss relative to 100 ohms

Ioff Current when 50 -50 mA Resulting DC current from a forced

powered off voltage. See note 3

Vrpp Voltage without 1.45 -0.25 V See note 4

damage

Table 11.2: TFI-5 Differential Input Characteristics

Notes 1. Magnitude of complex impedance with real part >0

2. Maximum of up to +/-50mv ground shift between transmit and receiver. If higher values in

ground shift are within the system, then AC coupling should be used.

3. Current after 10µS to any voltage between –0.05 and 1.45V if DC coupling allowed or

4. Receiver shall not be damaged within the voltage range (powered on or off), dV/dT changes

within this range are assumed to be below 1V/µS

5. For amplitude and rise/fall time requirements see the eye diagram of Figure 11.6.

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TrueRD2MVRDZtt2vttComplementGnd Figure 11.3 Termination and Signaling

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RxTFI-5DeviceConnectorTxV_TxV_Rx-0.05V < V_Rx < 1.45VdV/dT|max = 1v/µSResulting current after 10µS= +/-70mAGnd-0.05V < V_Tx < 1.45VdV/dT|max = 1v/µSResulting current after 10µS= +/-70mAPCBGnda) Devices that are DC Coupled or can be DC coupledRxTFI-5DeviceConnectorTxV_TxV_Rx-0.05V < V_Rx < 2.35VdV/dT|max = 1v/µSResulting current after 10µS= +/-70mAGnd-0.05V < V_Tx < 2.35VdV/dT|max = 1v/µSResulting current after 10µS= +/-70mAPCBGndb) Devices that are AC Coupled on the PCBExternal AC Cap's are to be 0.1µFRxTFI-5DeviceConnectorTxV_TxGnd-0.05V < V_Tx < 2.35VdV/dT|max = 1v/µSResulting current after 10µS= +/-70mAV_Rx-0.05V < V_Rx < 2.35VdV/dT|max = 1v/µSResulting current after 10µS= +/-70mAPCBGndc) Devices that are AC Coupled on the other PCBor could be AC coupledFigure 11.4 Idshort, Ioff & Vrpp Testing

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11.3 Jitter Requirements

11.3.1 Compliant Channel

A channel with crosstalk is compliant if it is capable of meeting the receiver eye mask as specified in Figure 11.6 and Table 11.3 as per CEI IA section 2.2.2, with the following conditions:

1. A single post tap transmitter, with less than or equal to 6dB of emphasis in the post tap

2. No Rx equalization

3. A transmit amplitude of 350 mVppd

4. Additional non-ISI DJ jitter of 0.175UIpp (emulating part of the Tx jitter, not including any effects of post tap)

5. Additional non-ISI RJ jitter of 0.175UIpp (emulating part of the Tx jitter) 6. A Tx edge rate filter: simple 20dB/dec low pass at 75% of baud rate 7. At a baud rate of 3.11 Gbps 8. At a BER of 10-12

11.3.2 Receive Eye Mask The receive eye mask specifies the jitter and amplitude at the receiver as shown in Figure 11.6. The horizontal limit specified in the eye mask shown in Table 11.3 represents the total jitter seen at the receiver input (both RJ and DJ). As per CEI IA section 2.2.4, the receiver shall tolerate at least the receiver eye template and jitter requirements as given in Table 11-3 with an additional sinusoidal jitter (Sj) as specified in section 11.4.

Figure 11.5 Receive Eye Mask

Differential signal amplitude [V] YR1

YR2 0

-YR2

-YR1

XR1 XR2 1-XR1 1 Normalized bit time [UI]

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XR1 (UI)

DJ [pp Total Jitter UI] [pp UI]

0.33 0.5 0.7 0.0875 0.37 0.65 XR2 (UI)

YR1 (V)

YR2 (V)

Table 11.3: Receive Eye Mask Specifications

Notes 1. XR1, XR2, YR1 and YR2 are defined in Figure 11.6 2. XR1 = Jtot/2

3. Receive eye mask is measured into a 100 ohm load with more than 20 dB return loss

between DC and 1.6 * baud rate.

4. Eye mask is the result of the jitter being passed through a single pole high pass filter with a

corner frequency of baudRate/1667.

5. RJ is calculated as being the difference between total jitter and deterministic jitter. 6. The receiver eye mask is for a Bit Error Ratio (BER) of 10-12

11.4 Wander Requirements

The receiver shall be able to tolerate sinusoidal jitter as defined in Figure 11.8 that is summed with the receive jitter when the receive Dj term is reduced by 0.1 UI.

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SJ Amplitude (UI)32 UI wrt. TFI8KREFBaudrate/166720dB/dec20MHz0.1UISJ Frequency

Figure 11.6 Sinusoidal Jitter allowable amplitude vs. frequency. Note that relative wander from one lane to another can be twice the absolute wander

of 32 UI shown in this diagram.

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12. Optical Interface Definition

This section describes the optical interface for TFI-5.

3\" FR4

ElectricalConnector

850nmVCSEL +Driver

OpticalConnector

100mMM 50um500MHz.km+ 2NPOconnector(1,5dB)

OpticalConnector

Pin +TIA +LA

ElectricalConnector

SerDes3\" FR4SerDes

ClockSourceClockSource

TP1TP1.5TP2TP3TP3.5TP4

Figure 12.1: Electro-optical inter-rack application model

Notes:

1. Pre-emphasis may have to be considered at the output of the SerDes in order to achieve the

jitter budget at TP2.

2. A possible hybrid inter-rack system with 30” FR4 as opposed to 3” FR4, would require a

retimer after the 30” conforming to the electrical specification of the intra-rack system.

Figure 12.1 shows the application model of the TFI-5 optical link, referred to as the inter-rack application. The TFI-5 optical interface utilizes vertical-cavity surface-emitting lasers (VCSEL) and a fiber cable to transmit the TFI-5 frame over distances of up to 100 meters. The fiber solution leverages the parallel fiber VCSEL-based technology currently being deployed in many optical backplane applications for digital cross-connect systems, terabit

routers and terabit switches. The target performance of the TFI-5 interface is to transmit data over 100 meters on standard 50-µm multimode fiber-ribbon cable.

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Parameter Min. Max Units Transmitter1

11Transmitter POUT (avg) -8 -2.5 dBm Transmitter OMA -7.2 dBm

830 860 Nm λc

0.85 nm ∆λrms

Trise/Tfall (20-80%) 130 ps RIN(OMA) -118 dB/Hz

2,3

Receiver Receiver PIN (avg) -2.5 dBm

4Receiver OMA -14 dBm 5PSTRESS OMA -11.5 dBm 830 860 nm λc

Return loss 12 dB Signal detect – asserted6 -17 dBm 6Signal detect – deasserted -30 dBm Table 12.1 Optical Interface Specifications

Notes:

1. All specifications are per channel and at the end of a 2 m patch cord. In the event of

accidental transmitter-to-transmitter connection, no damage shall occur that shall prevent the continued operation of the transmitter module within specification. Output power for

combined channels shall be compliant with IEC Class 1M laser safety requirements of IEC 60825-1, Amendment 2 (all channels aggregated). 2. All receiver specifications are per channel.

3. Receiver sensitivity shall be such that the BER ≤10-12 with the minimum optical power and

worst case extinction ratio.

4. Unstressed receiver sensitivity assuming no bandwidth penalties.

5. Assuming 2.5 dB penalty for jitter and clock and data recovery. Stressed receiver modulation

and stressed compliance signal vertical eye closure values are calculated theoretically and are informative.

6. Average signal power at worst-case extinction ratio. Signal detect signal is asserted when all

monitored channels are active. Signal is de-asserted when the optical power of one or more of the monitored channels drops below threshold.

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12.1 Optical cable, cable plant specification and link budget The optical fiber cabling model is shown in Figure 12.2. PMD

Fiber optic cabling ConnectRibbon ConnectRibbon Ribbon PMD ConnectConnectConnectConnectFigure 12.2 Fiber optic cabling model

. Each fiber shall carry a separate channel. The term channel is used for consistency with generic cabling standards.

Description min max unit Operating Wavelength 830 860 nm

7Symbol rate per channel 2.488 Gbaud Modal Bandwidth1 500 MHz·km Fiber attenuation at 850 nm 3.5 dB/km

3Channel Insertion Loss (connectors + fiber loss) 1.85 dB Link Power Budget 6.8 dB Jitter mask5 parameter W, [Dj] at test point 2 0.26 UI Jitter mask5 parameter σ [Rj 1 σ ] at test point 2 Jitter mask parameter W, [Dj] at test point 3 Jitter mask parameter σ [Rj 1 σ ] at test point 3 Operating range

16 0.26 18 100

mUI UI mUI m

Table 12.2 Multimode cable link power budget

1. Modal bandwidth at 830nm per TIA/EIA 455-204 or IEC 60793-1-40.

2. Link penalties are used for link budget calculations. These are not requirements and are not

to be tested.

3. Jitter mask according to IEEE 802.3ae 10G-BASE-SR.

4. Test points are defined in the application model. In addition TP2 must be measured after a

2m patch cord. See Figure 12.1 for the location of test point TP2 5. Jitter budgets are given in Appendix B.

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Appendix A: Mapping and Transport of ODU3 and 10gigE LAN PHY

The ODU3 and 10GE LAN mappings described here are simply proposals within the OIF and are potentially subject to standardization in other bodies. This material should be treated as informative only.

A.1 Asynchronous mapping of ODU3 into a C-4-272c for transport over 272 VC-4 / STS-3c’s The basic C-4-272c structure is comprised of 9 rows by 70720 (i.e. 272 x 260) columns. The extended ODU3 is mapped into this C-4-272c with the following structure (see Figure A.1):

1. Each of the nine rows is partitioned into 136 blocks, consisting of 520 octets each. 2. In each block, one negative justification opportunity octet (S) and five justification control bits (C) are provided. 3. Each block is partitioned into 5 sub-blocks, consisting of 104 octets each.

a. The first byte of each sub-block consists of a justification control byte (J), which consists o seven fixed stuff bits (bits R; bits 1 to 7) and a justification control bit (bit C, bit 8). b. The second byte of the last sub-block is a negative justification opportunity byte (S). c. The last 103 bytes of the first four sub-blocks consist of data bytes (D). d. The last 102 bytes of the last sub-block consist of data bytes (D). 4. Before the extended ODUk signal is mapped into the C-4-Xc, it is

scrambled using a self-synchronizing scrambler with polynomial X43 + 1. The scrambler operates over the whole ODUk frame and is not reset per frame. (See G.707 for details [5]). The set of five justification control bits (C) in every block is used to control the corresponding negative justification opportunity byte (S). CCCCC = 00000 indicates that the S byte is an information byte, whereas CCCCC = 11111 indicates that the S byte is a justification byte.

At the synchronizer all five C bits are set to the same value. Majority vote (3 out of 5) should be used to make the justification decision at the

desynchronizer for protection against single and double bit errors in the C bits.

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The value contained in the S byte when used as justification byte is all-ZERO's. The receiver is required to ignore the value contained in this byte whenever it is used as a justification byte.

The value contained in the R bits and bytes is all-ZERO's. The receiver is required to ignore the value contained in these bits/bytes.

When ODU or 10 GbE LAN PHY are transported via TFI-5 pointer justification is not needed. Any frequency alignment between the ODU or 10 GbE LAN PHY clock and the TFI-5 clock is done via the byte stuffing of the mapping process. Pointer justification should be avoided in this case in order to minimize the impact on jitter.

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121234567

520 octets520 octets520 octets520 octets520 octets520 octets520 octets520 octets520 octets

70720520 octets520 octets520 octets520 octets520 octets520 octets520 octets520 octets520 octets

5 sub blocks of 104 octets

103D

102D

103D: 103 Data octets102D: 102 Data octetsR: Fixed stuff

C: Justification Control

12345678RRRRRRRC

Figure A.1: Block structure for ODU3 mapping into C-4-272c

Figure A.2 details the mapping of ODU3 over the C-4-272c for transport through the TFI-5 system over 272 STS-3c / VC-4’s: the ODU3 is mapped into a single C-4-272c and this concatenated structure is column

disinterleaved and mapped into the 272 VC-4’s. The 272 VC-4’s generated in this way can be transported over any combination of TFI-5 links.

Figure A.3 details the demapping of an ODU3 from 272 VC-4’s. The 272 C-4’s are demapped from the 272 VC-4’s (received from any combination of TFI-5 links) and column interleaved to obtain the C-4-272c. The ODU3 is then demapped from the C-4-272c.

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Extended ODU3112...104105106.................38244MAPPING

C-4-272c1

JJJJJJ.............................................2

JJJJJJJJJ..........................................................

70449...70720

COLUMNDISINTERLEAVING

JJ9J1....104105106107....272273

J1B3C21J1B3C2G1F2G1F2H4F3K3N1H4F3K3VC-4 # 272Figure A.2: Mapping of ODU3 over C-4-272c for transport over 272 VC-4’s

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Implementation Agreement: OIF-TFI5-0.1.0 TFI-5 TDM Fabric to Framer Interface

J1B3261

1J1B3C2C2G1F2H4F3K3N1.....9

COLUMNINTERLEAVING

G1F2H4F3K3N1VC-4 # 272VC-4 # 111JJJJJJJ23...104105106107.................................................JJJJJJJJJ.............................................272273DEMAPPING

J9JC-4-272c70449...707201412...103104105.......................3824Extended ODU3Figure A.3: Demapping of an ODU3 from a C-4-272c transported over 272

VC-4’s

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A.2 Mapping of 10GE LAN PHY

A simple way to transport an IEEE 10 GE LAN PHY signal [8] through a TFI-5 system is by mapping the B66B 10Gbps Ethernet bit stream (10GBASE-xR) into a C-4-70c and transporting the C-4-70c over 70 STS-3c / VC-4’s. The mapping method is based on the ODU mapping into SONET/SDH as defined in [7].

Note that also a 10 GbE LAN PHY signal with 8B/10B line coding is defined (10GBASE-LX4). In order to map such a signal a 8B/10B to B/66B recoding is needed.

Table A.1 shows the structure used for mapping and the number of STS-3c/VC-4’s required for transport of a 10GE LAN PHY signal and the mapping efficiency of the described method.

Client Signal 10GE LAN PHY

Nominal Bit Rate (Mb/Sec) 10312.5

Mapped over C-4-70c

Transported using 70 VC-4’s

Mapping Efficiency 98.37%

Table A.1: Mapping of 10GE LAN PHY: format and efficiency Table A.2 shows the maximum and minimum client signal frequency deviation from the 10GE LAN PHY nominal frequency and the nominal justification ratio. Note that the bit rate tolerance of an 10 GE LAN PHY signal is only ±100ppm.

Minimum

frequency deviation from nominal

-1041

Maximum

frequency deviation from nominal

913

Nominal

Justification Ratio

Client signal 10GE LAN PHY

0.532738095

Table A.2: Mapping of 10GELAN PHY: rate adaptation

The basic C-4-70c structure is comprised of 9 rows by 18200 (i.e. 70 x 260) columns. The 10GE LAN PHY signal is mapped into this C-4-70c with the following structure (see Figure A.4):

1. Each of the nine rows is partitioned into 35 blocks, consisting of 520 octets each. 2. In each block, one negative justification opportunity octet (S) and five justification control bits (C) are provided.

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3. Each block is partitioned into 8 sub-blocks, consisting of 65 octets each.

a. The first byte of each sub-block consists of either:

i. A fixed stuff byte (R); or

ii. A justification control byte (J), which consists o seven fixed stuff bits (bits R; bits 1 to 7) and a justification control bit (bit C, bit 8).

b. The second byte of the last sub-block is a negative justification opportunity byte (S). e. The last bytes of the first seven sub-blocks consist of data bytes (D). f. The last 63 bytes of the last sub-block consist of data bytes (D). The set of five justification control bits (C) in every block is used to control the corresponding negative justification opportunity byte (S). CCCCC = 00000 indicates that the S byte is an information byte, whereas CCCCC = 11111 indicates that the S byte is a justification byte.

At the synchronizer all five C bits are set to the same value. Majority vote (3 out of 5) should be used to make the justification decision at the

desynchronizer for protection against single and double bit errors in the C bits.

The value contained in the S byte when used as justification byte is all-ZERO's. The receiver is required to ignore the value contained in this byte whenever it is used as a justification byte.

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CSI Code 1111 1111 1111 1111 1111 1110 1111 1101 1111 1100

0000 0001 0000 0000

Alarm/Condition TFI-5 Link Loss of Signal TFI-5 Link Loss of Frame Software Force - Away Software Local Fault Insert Software Force-To PMD Loss of Signal

PMA Loss of Synchronization PCS Loss of Block Lock PCS Remote Fault High Bit Error Rate Degraded Bit Error Rate No Alarm Reserved

Table A.3: : Client Status Indication (CSI) Coding for 10GE LAN PHY

clients. The value contained in the R bits and bytes is all-ZERO's. The receiver is required to ignore the value contained in these bits/bytes. •

The blank CSI code values are user programmable.

• Generation of the CSI byte for alarms/conditions with blank code points are application dependent. •

See Section 10.2.2 for the Connectivity Monitoring (CM byte).

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121234567

520 octets520 octets520 octets520 octets520 octets520 octets520 octets520 octets520 octets520 octets520 octets520 octets520 octets520 octets520 octets520 octets520 octets520 octets520 octets520 octets520 octets520 octets520 octets520 octets520 octets520 octets520 octets520 octets520 octets520 octets520 octets520 octets520 octets520 octets520 octets520 octets520 octets520 octets520 octets520 octets520 octets520 octets520 octets520 octets520 octets520 octets520 octets520 octets520 octets520 octets520 octets520 octets520 octets520 octets520 octets520 octets520 octets520 octets520 octets520 octets520 octets520 octets520 octets18200520 octets520 octets520 octets520 octets520 octets520 octets520 octets520 octets520 octets8 sub blocks of 65 octetsJDRDJDRDJDRDJDJS63DD: Data octets63D: 63 Data octetsR: Fixed stuffC: Justification Control

12345678RRRRRRRCFigure A.4: Block structure for 10GE LAN PHY mapping into C-4-70c

Figure A.5 details the mapping of 10GE LAN PHY over the C-4-70c for

transport through the TFI-5 system over 70 STS-3c / VC-4’s: the 10 GE LAN PHY signal is mapped into a single C-4-70c and this concatenated structure is column disinterleaved and mapped into the 70 VC-4’s. The 70 VC-4’s

generated in this way can be transported over any combination of TFI-5 links. Figure A.6 details the demapping of 10GE LAN PHY from 70 VC-4’s. The 70 C-4’s are demapped from the 70 VC-4’s (received from any combination of TFI-5 links) and column interleaved to obtain the C-4-70c. The 10GE LAN PHY signal is then demapped from the C-4-70c.

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10 GE LAN PHYn-1nn+1

n+n+65n+63

APPING

C-4-70c1JJJJJJ.............................................2

RRRRRRRRR..........................................................

18131...18200

COLUMNDISINTERLEAVING

JJ9J1....65666768687071

J1B31J1B3C2G1F2C2G1F2H4F3K3N1Figure A.5: Mapping of 10GE LAN PHY over C-4-70c for transport over 70

VC-4’s

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H4F3K3N1VC-4 # 70VC-4 # 1123261

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J1B3261

1J1B3C2C2G1F2H4F3K3N1.....9

COLUMNINTERLEAVING

G1F2H4F3K3N1VC-4 # 70VC-4 # 111JJJJJJJ23...656667686870.............................................RRRRRRRRR71.............................................DEMAPPING

J9JC-4-70c18131...18200n-1nn+1n+63n+65n+10 GE LAN PHYFigure A.6: Demapping of 10GE LAN PHY from a C-4-70c transported over 70 VC-4’s

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Appendix B: Jitter Notes

The following backplane physical assumptions for TFI-5 are used:

•Line -> Switch 9“+12“+9“ = 30”. For communications from a line card to a switch card, it is assumed that there are 9 inches of PCB trace on the line card, 12 inches on the FR-4.6 backplane, and another 9 inches on the switch card.•Line -> Line 3\" 24\" 3“ = 30”. For communications between two line cards, 3 inches are assumed on the line cards and 24 inches on the FR-4.6 backplane. The backplane is assumed to be composed of FR4-6 material, while the line and switch cards are assumed to contain FR4-2 material.Table B.1 shows a jitter budget for electrical intra-rack and electro-optical inter-rack

applications. Entries with green highlights are presented in Section 11 and 12 as normative figures. The other entries are informative.

Intra-rack (3.11Gbps)Test PointTP1TP1 to TP4TP4DJ0.1700.2000.370RJTJ0.3500.4100.7PlenaryInter-rack (3.11 Gbps)DJ0.1200.0200.1400.1200.2600.0000.2600.1100.3700.0300.400RJ0.1400.0000.1400.2000.2440.1500.2870.2300.3670.0000.367TJ0.2600.0200.2800.3200.5040.1500.70.3400.7370.0300.767TJ0.2600.0200.2800.2900.4800.1200.5110.2780.6630.0250.688 0.180 0.277 Plenary0.210Inter-rack (2.50 Gbps)TestPointTP1TP1 to TP1.5TP1.5TP1.5 to TP2TP2TP2 to TP3TP3TP3 to TP3.5TP3.5TP3.5 to TP4TP4DJ0.1200.0200.1400.1200.2600.0000.2600.0880.3480.0250.373 RJ 0.0000.2200.1400.140 0.170 0.1200.2510.190 0.3150.000 0.315 Table B.1: Jitter budget for electrical intra-rack and electro-optical inter-rack applications.

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Appendix C Sample Application

C.1 STS-1 Cross-connect

In this informative annex, a SONET/SDH STS-1 cross-connect system is discussed as a typical application for TFI-5 links. The main function of an STS-1 cross-connect system is to take an arbitrary STS-1 from any ingress SONET/SDH fiber and place it on an arbitrary STS-1 of any egress fiber. Many systems also support multi-cast. In which case, an ingress STS-1 is routed to several egress STS-1’s, possibly residing in multiple fibers. A

typical cross-connect has switching bandwidth of 100 Gbps to 1 Tbps. Future systems are expected to be bigger. Thus, the switching fabric is shown to be constructed from several switching devices.

...Switching FabricFramers(Rx Side)SwitchingDevice#1Framers(Tx Side)...OC-192Framer(Rx Side)SwitchingDevice#2OC-192Framer(Tx Side)OC-768Framer(Rx Side)SwitchingDevice#3OC-768Framer(Tx Side)Framers(Rx Side)... Figure C.1: STS-1 Cross-Connect Example Figure C.1 above shows an example STS-1 cross-connect system. For

clarity, the receive and transmit sections of the framers are drawn separately.

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The connections of an OC-192 and an OC-768 framer are shown in detail. The switching fabric is shown to consist of 4 switching devices, as a single device is unlike to have sufficient bandwidth to satisfy system requirements. Consider first the OC-192 framer. It sends 4 TFI-5 links towards the switching fabric and receives 4 links from the fabric. In order to minimize blocking, the links must be distributed to all 4 switching devices. If one concentrated all 4 framer links onto a single switching device, one would not be able to route between 2 framers unless they are both connected to the same switching device.

For systems that support multi-cast, it is necessary to balance which ingress STS-1 is sent to which switching device. Consider the example where STS-1’s number 1 to 48 from the OC-192 framer is to be broadcast to all egress fibers. If one were to route all 48 STS-1’s to the switching device #1, all data replication would occur inside that switching device. All the egress links of that switching device towards the transmit side of the framers would be consumed. The remaining ingress links of switching device #1 would unusable. One could either direct traffic away from switching device #1 or spread the multi-cast traffic over 4 TFI-5 links. Both solutions require flexible assignment of STS-1 to TFI-5 links.

The behavior of the OC-768 framer is very much analogous to that of the OC-192 framer. The only difference is that it sources a set 4 of links to each switching device and sinks a set of 4 links from each switching device. Load balancing applies among the 4 sets of links. Depending on the properties of the switching device, there may not be any requirement to load balance within each set of links.

Each switching device terminates a large number of ingress TFI-5 links and sources a large number of egress TFI-5 links. Being a TDM element, the switching device is synchronous. It requires that all the ingress links to be frame aligned and frequency locked to a common reference. One can see from Figure C.1, some ingress links originate from the same framer but the majority originates from many different framers. It is therefore necessary to limit skew, not just between links from a single framer, but also between links from different framers.

A similar situation also applies to the egress links between the switching devices and the framers. Each framer terminates links from all the switching devices. Processing can be greatly simplified if all the links are frequency locked and frame aligned. Otherwise, large de-skew FIFO's would be

required and delays would become undesirably large. Thus, TFI-5 requires that all links within a system to be frequency locked and frame aligned.

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Appendix D: Inter-Connect Characteristics

Connector Impedance

The recommended characteristic differential impedance of the connector(s) is to be 100Ω +/- 20%.

Characteristic Impedance

The recommended characteristic differential impedance of the channel

(including any connectors) is to be 100Ω with a return loss better than –10dB from near DC to 0.75 times the baud rate. The recommended single-ended impedance is to be 50Ω with a return loss better than –6dB from near DC to 0.75 times the baud rate.

Channel Model

Inter-connect Loss

This specification is intended as a point-to-point interface of 0 up to 75cm between integrated circuits using controlled impedance traces on low-cost printed circuit boards (PCBs). A simple model for PCB loss is given below [26].

4.34⎛RDC+RAC⎞

L*Att=αmetal+αdielectric=+GZo⎜⎟

2.⎝Zo⎠

⎞⎞2.3−4.34⎛ρ⎛10.75

⎟−⎜⎟*⎜Att=+f*f*tan(δ)*⎜⎟⎟⎜2.*Zo⎝W⎝t63µ⎠⎠2.

Where Zo is the characteristic impedance, W is the track width, tan(δ) is the

loss tan, t is the track thickness, f is the frequency in GHz, ρ is the sheet resistively, εr is the relative permittivity and Att is in dB/cm.

Table D.1 gives the attenuation for the PCB (does not include non-ideal vias or connectors) for the case of: Zo=50Ω, W=8mils and t=1oz (30µm).

εr

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FR4-2FR4-6FR4-13 Units

Loss Tan [27] 0.027 0.025 0.016

4.2 4.0 3.7

εr [27] Loss per cm (@1.6GHz) 0.08500.07730.0494 dB/cm

Loss @ 20cm 1.70 1.55 0.99 dB (@1.6GHz) Loss @ 75cm 6.38 5.80 3.71 dB (@1.6GHz)

Loss @ 1m (@1.6GHz) 8.50 7.73 4.94 dB Loss per cm (@3.2GHz) 0.16580.15040.0947 dB/cm

Loss @ 20cm 3.32 3.01 1. dB (@3.2GHz) Loss @ 75cm 12.44 11.28 7.10 dB (@3.2GHz)

Loss @ 1m (@3.2GHz) 16.58 15.04 9.47 dB Loss per cm (@5.5GHz) 0.28170.25520.1594 dB/cm

Loss @ 20cm 5.63 5.10 3.19 dB (@5.5GHz) Loss @ 75cm 21.13 19.14 11.96 dB (@5.5GHz)

Loss @ 1m (@5.5GHz) 28.17 25.52 15.94 dB

Table D.1 PCB Effects

Now one has to add in the losses for vias and connectors. At baud rate

divided by 2 typically one adds about 1dB per connector (assumes a “good” connector for that frequency of operation).

Also at baud rate divided by 2 one typically adds 0 to 6 dB for non-ideal vias and reflections. The value depends on the overall length, the type of

interconnect (micro-strip line or strip line, strip line typically being worse), return loss of Rx/Tx and transmission line, etc. Of note, the value is typically higher for shorter lengths (as reflections will not be reduced as much). Another popular way to spec the channel loss is to have an average or worse case “curve” fit to several real channels. This method includes effects of real vias and connectors (hence should give curves that are worse than the PCB model above). Both methods are useful (the PCB model to show the “best” case, and the curve fit model to show “some real design cases”). This method typically uses the equation below:

Att=−20*log(e)*a1*f+a2*f+a3*f2

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Where f is frequency in Hz, a1, a2, & a3 are the curve fit coefficients and Att is in dB. Table D.2 gives some examples of these coefficients. Figure D.1 shows various channel models along with the PCB model and a real 75cm backplane (with 5cm paddle cards on both ends).

XAUI [10] (50cm) 75cm [29] “Worse” 75cm [29] “Typical”

a1 a2 a3 3.3e-20 5.0e-20 3.5e-20

6.5e-6 2.0e-10 6.5e-6 3.9e-10 6.0e-6 3.9e-10

Table D.2 Curve fitting Coefficients

Figure D.1 Channel Models

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Appendix E: Cross Talk

Cross talk arises from coupling within the connectors, on the PCB, the package and the die. Cross talk can be categorized as either Near-End or Far-End Cross talk (NEXT and FEXT). In either of these categories, the amount of cross talk is dependent upon signal amplitudes, signal spectrum, and trace/cable length. There can be many aggressor channels onto one victim channel, however typically only a few are dominant.

A simplistic cross talk model (i.e. summation of all aggressor channels onto the one victim channel) would have a transfer function that rises at 20dB/dec from DC to some frequency Fz, and then flattens out till frequency Fp where it drops off. The slope at which it drops off is ill defined, but can be assumed to be either 20dB/dec or 0dB/dec (i.e. does not drop off) for modeling ease. The peak value of the transfer function is channel specific.

This standard assumes that the dominant cross talk can come from aggressors other than the transmitter associated with the receiver. Jitter caused by cross talk is bounded DJ, but can look like quite gaussian, and hence most measuring equipment will indicate it as RJ (thus multiplying the 1 sigma value by 14, hence over estimating the amount of jitter).

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Appendix F: Terms and Definitions Glossary

Here is a glossary of some acronyms used in the implementation agreement:

AISC-P Alarm Indication Signal Concatenation Indication—Path Layer AIS-L Alarm Indication Signal Line Layer AIS-P Alarm Indication Signal Path Layer EXC-MS Excessive Bit Error—Multiplexed Section Layer EXC-P Excessive Bit Error—Path Layer LOF Loss of Frame LOM Loss of MultiFrame LOS Loss of Signal OOF Out of Frame PDI Path Defect Indication PLM Payload Label Mismatch SD-L Signal Degrade—Line Layer SD-P Signal Degrade—Path Layer SF-L Signal Fail—Line Layer TIM-S Trace Identifier Mismatch—Section Layer UNEQ Unequipped AC Alternating current AIS Alarm indication signal AU Administrative unit BER Bit error ratio C-N Container of level N CID Connection identifier CM Connectivity monitoring DC Direct current FDI Forward defect indication GE Gigabit Ethernet INF In frame LAN Local area network OC-N Optical carrier of level N ODUN Optical channel data unit of level N OOF Out of Frame OTN Optical Transport Network PCB Printed circuit board PHY Physical interface CSI Client Status Indication SDH Synchronous Digital Hierarchy SOH Section overhead SONET Synchronous Optical Network SPE Synchronous payload envelop SPI-N System packet interface of level N STM-N Synchronous transport module of level N STS-N Synchronous transport signal of level N

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Correlated Wander

Components of wander that are common across all applicable in band signals.

Relative Wander

Components of wander that are uncorrelated between any two in band signals (SxI-5 Figure 4.1)

Total Wander

The sum of the correlated and uncorrelated wander. (See SxI-5 Figure 4,2)

Uncorrelated Wander

Components of wander that are not correlated across all applicable in band signals.

Wander

The peak to peak variation in the phase of a signal(clock or data) after filtering the phase with a single pole low pass filter with the –3db point at the wander corner frequency. Wander does not include skew.

Skew

The constant portion of the difference in the arrival time between the data of any two in-band signals.

End of Document

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