您的当前位置：首页正文

PT7A4410LJ资料

来源：华佗健康网

元器件交易网www.cecb2b.com

Data SheetPT7A4410/4410L

T1/E1/OC3 System Synchronizer

||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||

Features

•Supports AT&T TR62411 Stratum 3, 4 andStratum 4 Enhanced for DS1 interfaces and forETSI ETS 300 011, TBR 4, TBR 12, and TBR13 for E1 interfaces

•Supports ITU-T G.812 Type IV clocks for1.544kbit/s interfaces and 2.048kbit/s interface

•

Introduction

PT7A4410/4410L employs a digital phase-lockedloop (DPLL) to provide timing and synchronizingsignals for multitrunk T1 and E1 primary ratetransmission links, and for STS-3/OC3 links. The ST-BUS clock and framing signals are phase-locked toinput reference signals of either 2.048 MHz,1.544MHz or 8 kHz.

The PT7A4410/4410L meets the requirements forAT&T TR62411 Stratum 3, 4 and Stratum 4 En-hanced, and ETSI ETS 300 011 in jitter tolerance,jitter transfer, intrinsic jitter, frequency accuracy, hold-over accuracy, capture range, phase slope and MTIE,etc.

The PT7A4410/4410L operates in Manual or Auto-matic Mode, and in each of the modes, three operat-ing states are available: Normal, Holdover and Free-Run.

Provides C1.5, C3, C2, C4, C8, C6, C16 and C19output clock signals

Provides five kinds of 8kHz ST-BUS framingsignals

Two independent reference inputs

Input reference frequency 1.544MHz, 2.048MHzor 8kHz selectable

Provides bit error free reference switching andmeets phase slope and MTIE requirementsNormal, Holdover or Free-Run operating modesavailable

Holdover accuracy: ±0.2ppm

Automatic reference input impairment monitor

•

••

•

••

• Power supply: 5V (4410) and 3.3V(4410L)

Applications

•Synchronization and timing control for multitrunkT1 and E1 systems, STS-3/OC3 systems

••

Ordering Information

PartNumberPT7A4410JPT7A4410LJPackage44-PinPLCC44-PinPLCCST-BUS clock and frame pulse sourcesPrimary Trunk Rate Converters

PT0106(09/02)

Ver:0

元器件交易网www.cecb2b.com

Data SheetPT7A4410/4410L

T1/E1/OC3 System Synchronizer

Contents

Features.......................................................................................................................................................1Applications................................................................................................................................................1Introduction.................................................................................................................................................1Ordering Information..................................................................................................................................1Block Diagram............................................................................................................................................3Pin Information...........................................................................................................................................4

Pin Assignment.....................................................................................................................................4Pin Configuration.................................................................................................................................4Pin Description.....................................................................................................................................5Functional Description................................................................................................................................7

Overall Operation.................................................................................................................................7Modes and States of Operation...........................................................................................................10Applications Information....................................................................................................................14Detailed Specifications..............................................................................................................................16

Definitions of Critical Performance Specifictions...............................................................................16Absolute Maximum Ratings...............................................................................................................18Recommended Operating Conditions.................................................................................................18DC Electrical and Power Supply Characteristics................................................................................19AC Electrical Characteristics..............................................................................................................20Mechanical Specifications.........................................................................................................................33Note..........................................................................................................................................................34

PT0106(09/02)

Ver:0

元器件交易网www.cecb2b.com

Data SheetPT7A4410/4410L

T1/E1/OC3 System Synchronizer

Block Diagram

Figure 1. Block Diagram

RSTTCLRVCCGNDOSCiOSCoTCKTDITMSTRSTTDOPRISECMasterClockTIECorrectorVirtualReferenceDPLLAPLLIEEE 1149.1aStateSelectReferenceSelect MUXStateSelectInputImpairmentMonitorOutputInterfaceCircuitTIECorrectEnableACKiACKoC1.5C2C3C4C6C8C16C19F0F8F16RSPTSPRSELLOS1LOS2Mode/StateControl MachineGuardTimeCircuitFeedbackFrequencySelect MUXHOLDOVERMS1 MS2 GTo GTi FS1 FS2PT0106(09/02)

Ver:0

元器件交易网www.cecb2b.com

Data SheetPT7A4410/4410L

T1/E1/OC3 System Synchronizer

Pin Information

Pin Assignment

Table 1. Pin Assignment

GroupChipClockPower&GroundClockandFramingOutputsControlSignalsReferenceInputsIEEE1149.1aSymbolOSCi,OSCo,ACKi,ACKoVCC,AVDD,GND,AGNDC1.5,C3,C2,C4,C6,C8,C16,C19,F0,F8,F16,RSP,TSPRSEL,LOS1,LOS2,MS1,MS2,GTi,GTo,FS1,FS2,RST,TCLRPRI,SECTCK,TDI,TMS,TRST,TDOFunctionClockPowerClockandFramingSignalsControlReferenceClockIEEE1149.1aInterfacePin Configuration

Figure 2. Pin Configuration

6432144434241VCCOSCoOSCiAGNDF16RSPF0TSPF8C1.5AVDD405PRISECTRSTTCLRTCKGNDTMSRSTTDIFS1FS2789101112131415161720212223242526271819283938373644-Pin PLCC35343332313029TESTRSELMS1MS2TDOLOS1LOS2GToGNDGTiHOLDOVERPT0106(09/02)

C3C2C4C19ACKiGNDACKoC8C16C6VCCTop View4

Ver:0

元器件交易网www.cecb2b.com

Data SheetPT7A4410/4410L

T1/E1/OC3 System Synchronizer

Pin Description

Table 2. Pin Description

Pin1,23,3110234567,288911121314151617181920212224NameGNDAGNDTCKTCLRTRSTSECPRIVCCOSCoOSCiF16RSPF0TSPF8C1.5AVDDC3C2C4C19ACKiACKoTypeGroundDigitalGround(0V)GroundAnalogGroundIIIIIPowerOIOOOOOOPowerOOOOIOTestClock(TTLInput):ProvidestheclocktotheJTAGtestlogic.ThispinisinternallypulleduptoVCC.TIEcircuitreset(TTL):AlowlevelonthispinwillresettheTIEcircuit,re-aligningtheoutputsignalswiththeinputsignal.TCLRmustbeactive(low)foratleast300ns.ThispinisinternallypulleddowntoGND.TestReset(TTLInput):AsynchronouslyinitializestheJTAGTAPcontrollerbyputtingitintheTest-Logic-Resetstate.ThispinisinternallypulleddowntoGND.Secondaryreference(TTL):Oneoftwoindependentinputreferencesignals,internallypulleddowntoGND.Primaryreference(TTL):Theotherindependentreferencesignal,internallypulleddowntoGND.Powersupply+5VDCforPT7A4410J.+3.3VDCforPT7A4410LJOscillatormasterclockoutput(CMOS):Outputof20MHzmasterclockOscillatormasterclockinput(CMOS):Inputof20MHzmasterclock(canbeconnecteddirectlytoaclocksource)FramepulseST-BUS16.384Mb/s(CMOS):8kHzframesignalwith61nslowlevelpulsethatmarksthebeginningofaST-BUSframe,typicallyusedforST-BUSopetationat8.192Mb/s.Seefigure18.ReceiveSyncPulse(CMOSOutput).Thisisan8kHz488nsactivehighframingpulse,whichmarkstheendofanST-BUSframe.SeeFigure19.FramepulseST-BUS2.048Mb/s(CMOS):8kHzframesignalwith244nslowlevelpulsethatmarksthebeginningofaST-BUSframee,typicallyusedforST-BUSopetationat2.048Mb/s.Seefigure18.TransmitSyncPulse(CMOSOutput).Thisisan8kHz488nsactivehighframingpulse,whichmarksthebeginningofanST-BUSframe.SeeFigure19.FramepulseST-BUS8.192Mb/s(CMOS):8kHzframesignalwith122nshighlevelpulsethatmarksthebeginningofaST-BUSframe1.544MHzclock(CMOS):ThisoutputisusedinT1applications.AnalogPowerSupply:+5VDCforPT7A4410J.+3.3VDCforPT7A4410LJ3.088MHzclock(CMOS):ThisoutputisusedinT1applications.2.048MHzclock(CMOS):ThisoutputisusedforST-BUSoperationat2.048Mb/s.4.096MHzclock(CMOS):ThisoutputisusedforST-BUSoperationat2.048Mb/sand4.096Mb/s.Clock19.44MHz(CMOSOutput).ThisoutputisusedinOC3/STS-3applications.AnalogPLLClockInput(CMOSInput).ThisinputclockisareferenceforaninternalanalogPLL.ThispinisinternallypulleddowntoGND.AnalogPLLClockOutput(CMOSOutput).ThisoutputclockisgeneratedbytheinternalanalogPLL.DescriptionPT0106(09/02)

Ver:0

元器件交易网www.cecb2b.com

Data SheetPT7A4410/4410L

T1/E1/OC3 System Synchronizer

Table 2. Pin Description (continued)

Pin25262729NameC8C16C6HOLDOVERTypeOOOODescription8.192MHzclock(CMOS):ThisoutputisusedforST-BUSoperationat8.192Mb/s.16.384MHzclock(CMOS):ThisoutputisusedforST-BUSoperationwitha16.384MHzclock.Clock6.312MHz(CMOSOutput).ThisoutputisusedforDS2applications.Holdover(CMOSOutput).ThisoutputgoestoalogichighwheneverthedigitalPLLgoesintoholdovermode.GuardTime(Schmittinput):Thesignalatthispinisusedbythedevice’sstatemachineinbothManualandAutomaticmodestoeffecttheTIEfunctionandthestatechangesbetweenPrimaryHoldoverandPrimaryNormal,andPrimaryHoldoverandSecondaryNormal.RefertoTables6and7.ThesignalatthispinisclockedinbytherisingedgeofF8.GuardTime(CMOS):TheLOS1inputisclockedinbytherisingedgeofF8,thenbufferedandsenttoGTowheninAutomaticMode.ThispinistypicallyusedtodriveGTiinputthroughanRCcircuit.SecondaryReferenceLoss(TTL):Thispinisnormallyconnectedtoanexternalsourcethatapplieshighlogiclevelwheneverthesecondaryreferencesignalislostorinvalid.TheexistinglevelatthispinisclockedinbytherisingedgeofF8.ThispinisinternallypulleddowntoGND.PrimaryReferenceLoss(TTL):AhighlevelisappliedonthispinwhenthePrimaryreferencesignalislostorinvalid.RefertopindescriptionofLOS2.ThispinisinternallypulleddowntoGND.TestSerialDataOut(TTLOutput).JTAGserialdataisoutputonthispinonthefallingedgeofTCK.ThispinisheldinhighimpedancestatewhenJTAGscanisnotenable.Mode/ControlSelect2(TTL):AlongwithMS1,determinestheoperatingmodes(ManualorAutomatic)andoperatingstateswheninMaunalmode(Normal,HoldoverorFree-Run).Mode/ControlSelect1(TTL):RefertopindescriptionofMS2.ThispinisinternallypulleddowntoGND.ReferenceSourceSelect(TTL):InManualmode,lowlogiclevelatthispinselectsthePrimaryReferenceastheinputreferencesignalandahighlevelselectstheSecondary.ForAutomaticmode,thispinmustalwaysbemaintainedatlowlogiclevel.ThispinisinternallypulleddowntoGND.Test(TTLInput).Thisinputisnormallytiedlow.Whenpulledhigh,itenablesinternaltestmodes.ThispinisinternallypulleddowntoGND.FrequencySelect2(TTL):TogetherwithFS1,selectsoneofthethreeDPLLfeedbackfrequenciestomatchthedesiredInputReferenceFrequency(8kHz,1.544MHzor2.048MHz).FrequencySelect1(TTL):RefertothepindescriptionofFS2.TestSerialDataIn(TTLInput).JTAGserialtestinstructionsanddataareshiftedinonthispin.ThispinisinternallypulleduptoVCC..Reset(Schmitt):RSTResetsthedevicewhenatlowlogiclevel.Resetisneededwhenevertheoperatingmodeischanged,orthereferencesignalfrequencyisswitchedorwhenpower-up;soastoensureproperoperationofthedevice.FollowingReset,theoutputclocksandframesignalsarephase-alignedwiththeinputreferencesource.TestModeSelect(TTLInput).JTAGsignalthatcontrolsthestatetransitionsoftheTAPcontroller.ThispinisinternallypulleduptoVCC..30GTiI32GToO33LOS2I34353637LOS1TDOMS2MS1IOII38RSELI39404142TESTFS2FS1TDIIIII43RSTI44TMSIPT0106(09/02)

Ver:0

元器件交易网www.cecb2b.com

Data SheetPT7A4410/4410L

T1/E1/OC3 System Synchronizer

Functional Description

Overall Operation

The PT7A4410/4410L is a multitrunk synchronizer that pro-vides the clock and frame signals for T1 and E1 primary ratedigital transmission links, and STS-3/OC3 links.

It basically consists of the Clock Generator, Mode/State Con-trol Machine, Time Interval Error (TIE) Corrector, Digital Phase-Locked Loop (DPLL), Analog Phase- Locked Loop (APLL),Input Impairment Monitor and Output Interface Circuit.The DPLL circuit provides synchronization of the output sig-nals with any given input reference signal, and the TIE circuitensures phase continuity whenever the input reference signalsource is changed.

Referring to the block diagram on Page 3, the detailed func-tions of the PT7A4410/4410L are described as follows.Master Clock

The PT7A4410/4410L uses either an external clock source oran external crystal and a few discrete components with itsinternal oscillator as the master clock.Reference Select MUX

The PT7A4410/4410L accepts two independent reference sig-nals, the primary reference and secondary reference. Eitherone of them is selected by the Reference Select MUX circuitand sent to the TIE circuit. The selection is decided accordingto the availability and quality of the reference signals, themode operation, and State. Refer to Tables 3, 6 and 7.

Feedback Frequency Select MUX

The feedback frequency is selected by FS1 and FS2 (as shownin Table 3) to match the particular incoming reference fre-quency (1.544MHz, 2.048MHz or 8kHz). A reset (RST) mustbe performed after every frequency select input change. Table 3. Feedback Frequency Selection

FS20011FS10101InputFrequencyReserved8kHz1.544MHz2.048MHzTime Interval Error (TIE) Corrector

The purpose of the TIE corrector is to allow the phase of theoutput signals to be constant while switching between twomutually incoherent reference signal input sources. Whenevera new input reference signal is selected, the TIE corrector mea-sures the phase difference between it and the feedback signaland aligns them using a variable delay circuit. Thus, the TIECorrector output a virtual reference input signal for the DPLLthat has the same phase as it had for the previous referencesignal input source. Thus, the PT7A4410/4410L provides atotally seamless (“glitch-free”) transition from one referencesignal to another. The TIE Corrector diagram is shown in Fig-ure 3.

Figure 3. TIE Corrector

TCLRPRI or SECFromSelect MUXComparingCircuitDelay ValueProgrammableDelayCircuitVirtual ReferenceSignalTo DPLLFeedback SignalFromFrequency Select MUXTIE Corrector EnableFromMode/State MachinePT0106(09/02)

Ver:0

元器件交易网www.cecb2b.com

Data SheetPT7A4410/4410L

T1/E1/OC3 System Synchronizer

Whenever there is a change in the input reference source, suchas a switch from the primary reference signal (PRI) to second-ary reference signal (SEC), the typical result is a step change inphase of the DPLL input signal that causes an unacceptablestep change in the DPLL input signal phase. The TIE Correc-tor circuit is used to eliminate the step change in the DPLLinput signal phase, thus maintaining continuity of phase atthe DPLL output.

Referring to Figure 3, the selected reference signal (e.g. SEC)feeds the Comparing Circuit where it is compared with thefeedback signal from the output circuit. Whenever there is astep change in the reference input signal’s phase, the Compar-ing Circuit will generates a Delay Value for the ProgrammableDelay Circuit. The Delay Circuit then delays the input refer-ence signal by the Delay Value, thus providing the DPLL witha Virtual Reference Signal having no phase discontinuity.The DPLL phase detects and tracks the Virtual Reference Sig-nal. As the Virtual Reference Signal exhibits no discontinuityof phase, there is no phase transient in the DPLL output signal.This is the Normal operation of the device.

During the input reference signals source switching process, aholdover state will occurr before the DPLL begins to track theVirtual Reference Signal. When the input reference is switchedto the new source, the State Machine initiates Holdover State,during which the DPLL does not use the Virtual ReferenceSignal. Instead, it uses stored information to produce a clocksignal that is compared in the Comparing Circuit with theFeedback Signal. This compared result is sent to the Program-mable Delay Circuit which in turn delivers to the DPLL inputa new Virtual Reference Signal whose phase is aligned withthat of the previous input reference signal. The State Machinethen terminates Holdover State and return the device to Nor-mal state.

Figure 4. Block Diagram of DPLL

As the Programmable Delay Circuit maintains the phase of theVirtual Reference Signal while the TIE Corrector is enabled,there will in general be a time delay between the chip outputsignals and the selected input reference signal after switchingto a new input reference source (e.g. from PRI to SEC). Eachtime a new reference source is selected, there will in general bea new time delay. The value of this delay represents the accu-mulation of the phase errors measured and corrected for duringthe various reference source switching events.

The Programmable Delay Circuit can be zeroed through theTCLR pin (low level, min. duration 300ns), realigning theoutput signals with the present input reference signal. Thespeed of realignments is limited by the Limiter in the DPLL to5ns per 125µs. Convergence is in the direction of least phasetravel.

Digital Phase-Locked Loop (DPLL)

The DPLL consists of the Phase Detector, Limiter, Loop Filter,Digitally Controlled Oscillator (DCO) and Control Circuit.See Figure 4 for the block diagram of DPLL.

The Virtual Reference Signal from TIE is sent to Phase Detec-tor for comparison with the Feedback Signal from the Feed-back Frequency Select MUX. An error signal corresponding totheir instantaneous phase difference is produced and sent tothe Limiter.

The Limiter amplifies this error signal to ensure the DPLLresponds to all input transient conditions with a maximumoutput phase slope of 5ns per 125µs. This performance easilymeets the maximum phase slope of 7.6ns per 125µs or 81ns per1.326ms specified by AT&T TR62411.

The Loop Filter is a 1.9Hz low pass filter for all three referencefrequency selections: 8kHz, 1.544MHz and 2.048MHz. Thefilter ensures that the jitter transfer requirements in ETS 300-011 and AT&T TR62411 are met.

VirtualReferencefrom TIECorrectorPhaseDetectorLimiterLoopFilterDCODPLL ReferencetoOutput InterfaceCircuitControl CircuitFeedback SignalFromFrequency Select MUXState Select FromInput ImpairmentMonitorState SelectFromState MachinePT0106(09/02)

Ver:0

元器件交易网www.cecb2b.com

Data SheetPT7A4410/4410L

T1/E1/OC3 System Synchronizer

The Control Circuit uses signals from the State Machine andInput Impairment Monitor to control the operating states ofthe DPLL. Three states are available, Normal, Holdover andFree-Run.

The Error Signal, after limited and filtered, is sent to DigitallyControlled Oscillator. Based on the processed error value, theDCO will generate the corresponding digital output signalsfor the Tapped Delay Line in the Output Interface Circuit toproduce 12.352MHz, 12.624MHz, 19.44MHz and 16.384MHzsignals. The DCO synchronization method depends upon thePT7A4410/4410L operating state, as follows:

In Normal state, the DCO generates four output signals whichare frequency and phase locked to the selected input referencesignal.

In Holdover state, the DCO generates four output signals whosefrequencies are equal to what they were for a 30ms periodshortly before the end of the last Normal State.

In Free-Run state, the DCO is free running with an accuracyequal to that of the OSCi 20MHz source.Output Interface Circuit

The Output Interface Circuit consists of the Tapped Delay Linesand E1/T1 Dividers as shown in Figure 5.

Signals from the DCO are sent to Tapped Delay Lines to gener-ate four clock signals, 16.384MHz, 12.624MHz, 19.44MHzand 12.352MHz, which are divided in the T1 and E1 Dividersrespectively to provide needed clock and frame signals.The T1 Divider uses the 12.352MHz signal to generate twoclock signals, C1.5 and C3. They have a nominal 50% dutycycle.

The DS2 Divider uses 12.624MHz signal to generate clocksignal C6.

Clock signal C19 is generated from 19.44MHz by tapped De-lay Line.

The E1 Divider uses the 16.384MHz signal to generate fourclock signals and three frame signals, i.e., C2, C4, C8, C16,F0, F8 and F16. The frame signals are generated directly fromthe C16 signal.The C2, C4, C8 and C16 signals have nominal 50% duty cycle.All the frame and clock outputs are locked to each other for alloperating states. They have limited driving capability andshould be buffered when driving high capacitance (e.g., 30pF)loads.

Figure 5. Block Diagram of Output Interface Circuit

TappedDelayLine12.352MHzT1DividerC1.5C3SignalFromDCOTappedDelayLine16.384MHzE1DividerC2C4C8C16F0F8F16RSPTSPC6TappedDelayLineTappedDelayLine12.624MHzDS2Divider19.44MHzC19ACKiAPLLACKoPT0106(09/02)

Ver:0

元器件交易网www.cecb2b.com

Data SheetPT7A4410/4410L

T1/E1/OC3 System Synchronizer

Mode/State Control Machine

The Mode/State Control Machine determines whether thePT7A4410/4410L operates in Automatic or Manual mode, andwhether it is in the Normal, Holdover or Free-Run state. InAutomatic Mode, the PT7A4410/4410L selects one of threestates, Normal, Holdover or Free-Run State. The sequence isdetermined by LOS1, LOS2 and GTi signals. In Manual Mode,a single state of operation is selected, in accordance with theMS1, MS2, GTi and RSEL signals.

All mode and state changes are synchronous with the risingedge of F8. See the Modes and States of Operation section forcomplete details.Guard Time Circuit

The Guard Time Circuit sends control signal (GTi) to Mode/State Control Machine for control of Modes and States. It hastwo functions:

- enabling/disabling the TIE Corrector (Manual and Au- tomatic) (Refer to Table 6 and 7);

- selecting which mode change takes place (Automatic only).

Under Automatic Mode and in Primary Normal State, two statechanges are possible (not counting Auto-Holdover). They are: - Primary Normal to Primary Holdover, and - Primary Normal to Secondary Normal.

The level at the GTi pin determines which state occurs. When - GTi=0, Primary Normal to Primary Holdover, - GTi=1, Primary Normal to Secondary Normal.Input Impairment Monitor

This circuit monitors the input signals to the DPLL and auto-matically enables the Holdover State (Auto-Holdover) whenthe incoming signal is completely lost, or if its frequency isoutside the auto-holdover capture range (either a small or largeamount). When the incoming signal returns to normal, theDPLL will be returned to Normal State.The Auto-Holdover circuit does not use TIE correction. There-fore, the phase delay between the input and output after switch-ing back to Normal State is preserved (is the same as just priorto the switch to Auto-Holdover).APLL

The analog PLL is intended to be used to achieve a 50% Dutycycle output clock. Connecting C19 to ACKi will generate aphase locked 19.44 MHz ACKo output with a nominal 50%duty cycle and a maximum peak-to-peak unfiltered jitter of0.174 U.I. . The analog PLL has an intrinsic jitter of less than0.01 U.I. In order to achieve this low jitter level separate pinsare provided to power (AVDD, AGND) the APLL.

Modes and States of Operation

The PT7A4410/4410L operates either in Manual mode or Au-tomatic mode. Each mode has three possible operating states,Normal, Holdover or Free-Run.

Shown in Table 4 and Table 5 are the mode and state selectioninstructions, using pins MS1, MS2, and RSEL. Table 4. Input Reference Selection

ModesManualRSEL0101InputReferencePRISECMode/StateMachineControlReservedAuto Table 5. Operation Modes and States

MS2001MS10101ModesManualManualManualAutoStatesNormalHoldoverFreerunMode/StateMachineControl Figure 6. Block Diagram of Mode/State Control MachineTo ReferenceSelect MUXRSELLOS1LOS2To Tie CorrectorEnableTo DPLLState SelectTo and FromGuard TimeCircuit1Mode/StateControl MachineMS1MS2HOLDOVERPT0106(09/02)

Ver:0

元器件交易网www.cecb2b.com

Data SheetPT7A4410/4410L

T1/E1/OC3 System Synchronizer

Manual Mode

The Manual Operation Mode is used when either very simplecontrol is required, or when complex control is required whichis not accommodated by Automatic Mode. For example,Manual Mode can be used in a system requiring only NormalState and only one input stimulus (RSEL). Complex control isused for systems requiring states of operation and more inputstimuli. In such cases, external circuitry, typically amicrocontroller, is needed.

In Manual Mode, one of the three states is selected by MS2and MS1. The active reference input is selected by the RSELpin. See Table 4 and Table 5. For the state change situation,refer to Table 6 and Figure 7.Automatic Mode

Automatic Mode is used in systems requiring neither verysimple nor very complex control, which can be realized by thePT7A4410/4410L in accordance with the State Change Dia-gram shown in Figure 8.

Automatic Mode is also selected by MS2 and MS1 (set 1,1). Inthis Mode, the PT7A4410/4410L will operate in three statesalternatively. The changes of states will follow a sequenceautomatically under control of LOS1, LOS2 and GTi. See Table7 and Figure 8 for the state change sequence.Normal State

In Normal State, the PT7A4410/4410L output signals are syn-chronized with one of two input reference inputs.

In this state, the input reference signal is used, with or withoutTIE correction, as reference for the DPLL phase detector.

Holdover State

In Holdover State, the output signals of PT7A4410/4410L arenot synchronized with the external input reference signal. In-stead, they are generated by using the information stored 30msto 60ms before when the device operated in Normal State.When in Normal Mode, a numerical value corresponding tothe output reference frequency is stored alternately in twomemory locations every 30ms. When the device is switchedinto Holdover state, the value in memory from (between 30msand 60ms) is used to set the output frequency of the device.Generally, the amount of phase drift while in Holdover is neg-ligible because the Holdover State is very accurate. Two fac-tors affect the accuracy of Holdover State. One is drift on theMaster Clock while in Holdover State. The change in OSCiaccuracy while in Holdover, other than absolute Master Clock(OSCi) accuracy, will affect the holdover accuracy. The otherfactor is large jitter on the reference input prior (30 to 60ms) tothe mode switch.

The Holdover State is generally used for short durations, un-der control of GTi signal, when the synchronization to theinput reference is temporarily disturbed.Free-Run State

Typically the Free-Run State is used when a master clock isrequired or immediately following system power-up beforenetwork synchronization is achieved.

In Free-Run State, the outputs of the PT7A4410/4410L areuncorrelated with the input reference signal and the storedinformation of output reference. Instead, these output signalsare based solely on the master clock frequency (OSCi). Theaccuracy of the output clock is equal to the accuracy of themaster clock (OSCi).

PT0106(09/02)

Ver:0

元器件交易网www.cecb2b.com

Data SheetPT7A4410/4410L

T1/E1/OC3 System Synchronizer

Table 6. Manual Operation Mode

InputControlFree-RunMS2000001MS1000110RSEL00101XGTiS001XXXXS1S1S2//-Normal(PRI)S1--S2TIES1H/S0StateNormal(SEC)S2S1TIES1TIE-/S2HS0Holdover(PRI)S1HS1S1TIES2TIE-/S0Holdover(SEC)S2HS1TIES1TIES2TIE/-S0Legend:-:Nochange/:NotvalidTIE:StatechangeoccurswithTIECorrectorcircuit.Refertofigure6forstatechangestoandfromAuto-Holdoverstate. Figure 7. Diagram of State Change in Manual Mode

S0Free-Run(10X)S1NormalPrimary(000)IRS1AAuto-HoldoverPrimary(000)S2AAuto-HoldoverSecondary(001)IRS2NormalSecondary(001)GTi=1GTi=0S1HHoldoverPrimary(010)S2HHoldoverSecondary(011)Notes:(xxx): (MS2 MS1 RSEL) * Movement to Normal State from any state requires aIR: Invalid Reference Signal valid input signal. : Phase re-alignment : Phase continuity maintained without TIE Corrector : Phase continuity maintained with TIE CorrectorPT0106(09/02)

Ver:0

元器件交易网www.cecb2b.com

Data SheetPT7A4410/4410L

T1/E1/OC3 System Synchronizer

Table 7. Automatic Operation Mode (MS1 MS2=11, RSEL=0)

InputControlFree-RunLOS21XX001LOS1100111GTiX0101XRSTS00to111111-S1S1S2S2-Normal(PRI)S1S0--S1HS2TIES1HStateNormal(SEC)S2S0S1TIES1TIE--S2HHoldover(PRI)S1HS0S1S1TIE-S2TIE-Holdover(SEC)S2HS0S1TIES1TIES2TIES2TIE-Legend:-:Nochange/:NotvalidTIE:StatechangeoccurswithTIECorrectorcircuit.Refertofigure7forstatechangestoandfromAuto-Holdoverstate. Figure 8. Diagram of State Change in Automatic Mode

(11X)(11X) RST=1Reset(X0X)(X0X)S0Free-Run(011)(01X)(01X)(X0X)(X0X)(01X)S1NormalPrimaryIRS1AAuto-HoldoverPrimary(X0X)(011)(X0X)S2AAuto-HoldoverSecondaryIRS2NormalSecondary(011)(11X)(X01)(X00)(010 or 11X)(010 or 11X)(11X)(01X)S1HHoldoverPrimaryS2HHoldoverSecondary(11X)(010 or 11X)Notes:(xxx): (LOS2 LOS1 GTi) * Movement to Normal State from any state requires aIR: Invalid Reference Signal valid input signal. : Phase re-alignment : Phase continuity maintained without TIE Corrector : Phase continuity maintained with TIE CorrectorPT0106(09/02)

Ver:0

元器件交易网www.cecb2b.com

Data SheetPT7A4410/4410L

T1/E1/OC3 System Synchronizer

Applications Information

Master Clock

The PT7A4410/4410L uses either an external clock source oran external crystal as the master timing source.

In Free-Run State, the frequency tolerance of the PT7A4410/4410L output clocks are equal to the frequency tolerance ofthe timing source. In an application, if an accurate Free-RunState is not required, the tolerance of the master timing sourcemay be 100ppm. If required, the tolerance must be no greaterthan 32ppm.

The capture range of PT7A4410/4410L will also be consid-ered when deciding the accuracy of the master timing source.The sum of the accuracy of the master timing source and thecapture range of the PT7A4410/4410L will always equal230ppm. For example, if the master timing source is 100ppm,the capture range will be 130ppm.• Clock Oscillator

If using an external clock source, its output pin should beconnected directly (not AC coupled) to the OSCi pin of thePT7A4410/4410L and the OSCo pin of PT7A4410/4410L canbe left open as shown in Figure 9 or connected as an outputpin.

• Crystal Oscillator

If a crystal oscillator is selected as the master timing source, itshould be connected to the PT7A4410/4410L as shown inFigure 10.

Figure 10. Crystal Oscillator Connection

PT7A4410/4410LOSCi20MHz1MΩ56pF39pF3-50pFOSCo100ΩThe crystal specification is as follows:- Frequency:- Tolerance:

- Oscillation Mode:- Resonance Mode:- Load Capacitance:

- Maximum Series Resistance:- Αpproximate Drive Level:Guard Time Adjustment Circuit

20MHzas requiredFundamentalParallel32pF35Ω1mW

Figure 9. Clock Oscillator Connection

PT7A4410/4410LOSCi+5V+5V20MHz OUTGND0.1µFAT&T TR62411 recommends that excessive switching of thetiming reference should be minimized. Switching between ref-erences should be performed only when the primary signal isdegraded.

The Holdover State is used to minimize reference sourceswitching (from PRI to SEC). When the PRI signal is degraded,the PT7A4410/4410L enters Holdover State for a predeter-mined maximum time (i.e., guard time). If the PRI signal re-turns to normal before the expiration of the guard time (levelat GTi pin is low), the PT7A4410/4410L will return to NormalState with PRI input reference. If the PRI signal is still de-graded after expiration of the guard time (level at GTi be-comes high), the reference switching (from PRI to SEC) willoccur.

OSCoNo ConnectionWhen selecting the clock oscillator, following specificationsshould be considered. They are- absolute frequency

- frequency change over temperature- output rise and fall time- output level- duty cycle

Refer to AC Electrical Characteristics.

PT0106(09/02)

Ver:0

元器件交易网www.cecb2b.com

Data SheetPT7A4410/4410L

T1/E1/OC3 System Synchronizer

A simple way to control the Guard Time is shown in Figure 11.The Guard Time can be calculated as follows: VCC

tGd = RC x ln ( ) ≅ RC x 0.6 VCC - VSIH

* VSIH is the logic high going threshold for the GTi Schmitt Triggerinput, see DC Electrical Characteristics.

In cases where fast toggling of the LOS1 input might be ex-pected, an unsymmetrical Guard Time Circuit is recommendedas shown in Figure 12. This setting ensures that referenceswitching does not occur until the entire guard time has ex-pired. The timing diagram is shown in Figure 13.

Figure 11. Symmetrical Guard Time Circuit

PT7A4410/4410L Figure 12. Unsymmetrical Guard Time Circuit

PT7A4410/4410LGToRC150kΩ+C10µFRD1kΩGToR150kΩ+C10µFGTiRP1kΩGTiRP1kΩ Figure 13. Timing Example of Unsymmetrical Guard Time Circuit in Automatic Mode

SECSignalStatusLOS2PRISignalStatusLOS1GoodGoodBadTDGoodTDBadGoodGToVSIHGTiStatePRINormalPRIHoldoverPRINormalPRIHoldoverSECNormalPRINormalPT0106(09/02)

Ver:0

元器件交易网www.cecb2b.com

Data SheetPT7A4410/4410L

T1/E1/OC3 System Synchronizer

Reset Circuit

A simple power up reset circuit with about a 50µs reset active(low) time is shown in Figure 14. Resistor RP is for protectiononly. The reset low time is not critical but should be greaterthan 300ns.

Figure 14. Power-up Reset Circuit

PT7A4410/4410LDetailed Specifications

Definitions of Critical Performance Specifictions

Intrinsic Jitter: Intrinsic jitter is the jitter produced by thesynchronizing circuit. It is measured by applying a referencesignal with no jitter to the input of the device, and measuringits output jitter. Intrinsic jitter may also be measured when thedevice is in a non-synchronizing mode - such as free runningor holdover - by measuring the output jitter of the device.Intrinsic jitter is usually measured with various band limitingfilters depending on the applicable standards.

Jitter Tolerance: Jitter tolerance is a measure of the ability ofa PLL to operate properly (i.e., remain in lock and/or regainlock in the presence of large jitter magnitudes at various jitterfrequencies) when jitter is present on its reference. The appli-cable standard specifies how much jitter to apply to the refer-ence when testing for jitter tolerance.

Jitter Transfer: Jitter transfer or jitter attenuation refers to themagnitude of jitter at the output of a device with respect to agiven amount of jitter at the input of the device. Input jitter isapplied at various amplitudes and frequencies, and output jit-ter is measured with various filters depending on the appli-cable standards.

Its 3 possible input frequencies and 9 outputs give thePT7A4410/4410L 27 possible jitter transfer combinations.However, only three cases of the jitter transfer specificationsare given in the AC Electrical Characteristics; as the remainingcombinations can be derived from them.

For the PT7A4410/4410L, two internal elements determinethe jitter attenuation. They are internal 1.9Hz low pass loopfilter and phase slope limiter. The phase slope limiter limitsthe output phase slope to 5ns/125µs. Therefore, if the inputsignal exceeds this rate, such as for very large amplitude lowfrequency input jitter, the maximum output phase slope willbe limited (i.e., attenuated) to 5ns/125µs.

It should be noted that 1UI at 1.544MHz (644ns) is not equalto 1UI at 2.048MHz (488ns). A transfer value using differentinput and output frequencies must be calculated in commonunits (e.g., seconds) as shown in the following example.Example : When the T1 input jitter is 20UI (T1 UI Units) andthe T1 to T1 jitter attenuation is 18dB, The T1 and E1 outputjitter can be calculated as follows:

+5VR10kΩRP1kΩC10nFRSTPower Supply Decoupling

The PT7A4410/4410L has two VCC pins and two GND pins.Power decoupling capacitors should be included as shown inFigure 15.

Figure 15. Power Supply DecouplingC20.1µF+2831PT7A4410/4410L17+1017+C30.1µFC10.1µFPT0106(09/02)

Ver:0

元器件交易网www.cecb2b.com

Data SheetPT7A4410/4410L

T1/E1/OC3 System Synchronizer

-A( )20

-18

( )20

JT1o = JT1i x 10 = 20 x 10 = 2.5UI644ns1UIT1 JE1o = JT1o x ( ) = Jx ( ) = 3.3UIT1o

1UIE1

488ns

Using the above method, the jitter attenuation can be calcu-lated for all combinations of inputs and outputs based on the

three jitter transfer functions provided.

Note that the resulting jitter transfer functions for all combina-tions of inputs (8kHz, 1.544MHz, 2.048MHz) and outputs(8kHz, 1.544MHz, 2.048MHz, 4.096MHz, 8.192MHz,16.384MHz, 6.312MHz, 19.44MHz) for a given input signal(jitter frequency and jitter amplitude) are the same.

Since intrinsic jitter is always present, jitter attenuation willappear to be lower for small input jitter signals than for largeones. Consequently, accurate jitter transfer function measure-ments are usually made with large input jitter signals (e.g.,75% of the specified maximum jitter tolerance).

Frequency Accuracy: Frequency accuracy is defined as theabsolute tolerance of an output clock signal when it is notlocked to an external reference, but is operating in a free run-ning mode. For the PT7A4410/4410L, the Free-Run accuracyis equal to the Master Clock (OSCi) accuracy.

Holdover Accuracy: Holdover accuracy is defined as the ab-solute tolerance of an output clock signal, when it is not lockedto an external reference signal, but is operating using storagetechniques. For the PT7A4410/4410L the storage value is de-termined while the device is in Normal State and locked to anexternal reference signal. The absolute Master Clock (OSCi)accuracy of the PT7A4410/4410L does not affect Holdoveraccuracy, but the change in OSCi accuracy while in HoldoverMode does.

Lock Range: If the PT7A4410/4410L DPLL is already in astate of synchronization (“lock”) with the incoming referencesignal, it is able to track this signal to maintain lock as itsfrequency varies over a certain range, called the Lock Range.The size of Lock Range is related to the range of the DigitallyControlled Oscillators and is equal to 230ppm minus the ac-curacy of the master clock (OSCi). For example, a 32ppm mas-ter clock results in a Lock Range of 198ppm.

Capture Range: The PT7A4410/4410L DPLL is not at presentin a state of synchronization (lock) with the incoming referencesignal, it is able to initiate (acquire) lock only if the signal’s fre-quency is within a certain range, called the Capture Range. Forany PLL, no portion of the Capture Range can fall outside theLock Range, and, in general, the Capture Range is more narrowthan the Lock Range. However, owing to the design of its PhaseDetector, the PT7A4410/4410L’s Capture Range is equal to itsLock Range.

Phase Slope: Phase slope is measured in seconds per secondand is the rate at which a given signal changes phase withrespect to an ideal signal of constant frequency. The givensignal is typically the output signal. The ideal signal is ofconstant frequency and is nominally equal to the value of thefinal output signal or final input signal.

Time Interval Error (TIE): TIE is the time delay between agiven timing signal and an ideal timing signal.

Maximum Time Interval Error (MTIE): MTIE is the maxi-mum peak to peak delay between a given timing signal and anideal timing signal within a particular observation period. MTIE(S) = TIEmax(t) - TIEmin(t)

Phase Continuity: Phase continuity is the phase differencebetween a given timing signal and an ideal timing signal atthe end of a particular observation period. Usually, the giventiming signal and the ideal timing signal are of the same fre-quency. Phase continuity applies to the output of the synchro-nizer after a signal disturbance due to a reference source switchor a state change. The observation period is usually the timefrom the disturbance, to just after the synchronizer has settledto a steady state.

For the PT7A4410/4410L, the output signal phase continuityis maintained to within 5ns at the instance (over one frame) ofall reference source switches and all state changes. The totalphase shift, depending on the switch or type of state change,may accumulate up to 200ns over many frames. The rate ofchange of the 200ns phase shift is limited to a maximum phaseslope of approximately 5ns/125µs. This meets the AT&TTR62411 maximum phase slope requirement of 7.6ns/125µs(81ns/1.326ms).

PT0106(09/02)

Ver:0

元器件交易网www.cecb2b.com

Data SheetPT7A4410/4410L

T1/E1/OC3 System Synchronizer

Absolute Maximum Ratings

Note:

Stresses greater than those listed under MAXIMUMRATINGS may cause permanent damage to thedevice. This is a stress rating only and functionaloperation of the device at these or any other condi-tions above those indicated in the operational sec-tions of this specification is not implied. Exposureto absolute maximum rating conditions for ex-tended periods may affect reliability.

Storage Temperature......................................................-65oC to +150oCAmbient Temperature with Power Applied......................-40oC to +85oCSupply Voltage to Ground Potential (Inputs & VCC Only)......-0.3 to 7.0VSupply Voltage to Ground Potential (Outputs & D/O Only)..-0.3 to 7.0VDC Input Voltage..................................................................-0.3 to 7.0VDC Output Current......................................................................120mAPower Dissipation.......................................................................900mW

Recommended Operating Conditions

Table 8. Recommended Operating Conditions

SymDescriptionSupplyVoltagefor4410VCCSupplyVoltagefor4410LTAOperatingTemperatureOverRecommendedOperatingConditionsTestConditionsMin4.53.0-40Typ5.03.325Max5.53.685UnitsVVoCPT0106(09/02)

Ver:0

元器件交易网www.cecb2b.com

Data SheetPT7A4410/4410L

T1/E1/OC3 System Synchronizer

DC Electrical and Power Supply Characteristics

Table 9. DC Electrical and Power Supply Characteristics

SymICCQDescriptionQuiescentPowerSupplyCurrentDevice44104410L4410ICCSupplyCurrent4410L44104410LVIHVILVCIHVCILVSIHTTLHIGHInputVoltage-AllpinsexceptOSCi,RSTandGTiTTLLOWInputVoltage-AllpinsexceptOSCi,RSTandGTiCMOSHIGHInputVoltage-OSCipinCMOSLOWInputVoltage-OSCipinSchmittHIGHInputVoltage-GTi,RSTpinsSchmittLOWInputVoltage-GTi,RSTpinsSchmittHysteresisVoltage-GTi,RSTpinsInputLeakageCurrent-Pins:TCK,SEC,PRI,TDI,TMSIILInputLeakageCurrent-Pins:TCLR,TRST,ACKi,LOS2,LOS1,MS1,RESL,TESTInputLeakageCurrent-otherpinsVOHVOLHIGHOutputVoltageLOWOutputVoltage44104410LIOH=-4mAIOL=4mA44104410L44104410L-102.42.00.8VI=VCCor0V44104410L44104410L0.4-140-100140100103.62.61.81.10.7VCC0.3VCCTestConditionsOSCi=0V,Note2MinTypMax2010603570402.00.8UnitsmAmAmAmAmAmAVVVVVVVVVµAµAµAµAµAVVVOSCi=Clock,Note2OSCi=Crystal,Note2VSILVHYSNote:

1. Supply voltages and operating temperature are as per Recommended Operating Conditions.2. MS2 = VCC, FS1 = VCC , FS2= GND, other inputs connected to GND.3. All outputs are unloaded except for VOH and VOL measurement.

PT0106(09/02)

Ver:0

元器件交易网www.cecb2b.com

Data SheetPT7A4410/4410L

T1/E1/OC3 System Synchronizer

AC Electrical Characteristics

Performance

Table 10. Performance

SymDescription0ppmFree-RunStateAccuracywithOSCiat:32ppm100ppm0ppmHoldoverStateAccuracywithOSCiat:32ppm100ppm0ppmDPLLCaptureRangeWithOSCiat:32ppm100ppmAPLLCaptureRangePhaseLockTimeOutputPhaseContinuitywith:ReferenceSwitch431-3,6-141-3,6-141-2,4-141-4,6-141-3,6-141-3,6-81,2,4,6-8,405-8TestConditions*Min0-32-100-0.2-0.2-0.2-190-158-9010TypMax0+32+100+0.2+0.2+0.2+230+198+1303023200200200506001-14,27OutputPhaseSlope8kHzReferenceInputforAuto-Holdoverwith:1.544MHz2.048MHz1-3,6,9-111-3,7,9-111-3,8-11<-30k<-30k<-30kororor45>+30k>+30k>+30kµs/sppmppmppmUnitsppmppmppmppmppmppmppmppmppmMHzsnsnsnsnsnsStateSwitchtoNormalStateSwitchtoFree-RunStateSwitchtoHoldoverMTIE(MaximumTimeIntervalError)* Refer to the Test Conditions on Page 32 for details.

PT0106(09/02)

Ver:0

元器件交易网www.cecb2b.com

Data SheetPT7A4410/4410L

T1/E1/OC3 System Synchronizer

Voltage Levels for Timing Parameter Measurement

Table 11. Voltage Levels for Timing Parameter Measurement

SymVTVHMVLMDescriptionThresholdVoltageRisingandFallingThresholdVoltageHighRisingandFallingThresholdVoltageLowSchmitt0.5VCC0.7VCC0.3VCCTTL1.52.00.8CMOS0.5VCC0.7VCC0.3VCCUnitsVVV Figure 16. Voltage Levels for Timing Parameter Measurement

Timing Reference PointsSignalVHMVTVLMtIF.tOFtIR.tORPT0106(09/02)

Ver:0

元器件交易网www.cecb2b.com

Data SheetPT7A4410/4410L

T1/E1/OC3 System Synchronizer

Input and Output Timing

Table 12. Input and Output Timing of 4409

SymtRWtIRFtR8DtR15DtR2DtF0DtF16DtC15DtC6DtC3DtC2DtC4DtC8DtC16DtTSPDtRSPDtC19DtC15WtC3WtC6WtC2WtC4WtC8WDescriptionReferenceInputpulseWidthHighorLowTestConditions*1-3,6-11,39Min100TypMaxUnitsnsReferenceInputRisingorFallingTime8kHzReferenceInputtoF8Delay1.544kHzReferenceInputtoF8Delay2.048kHzReferenceInputtoF8DelayF8toF0DelayF8toF16DelayF8toC1.5DelayF8toC6DelayF8toC3DelayF8toC2DelayF8toC4DelayF8toC8DelayF8toC16DelayF8toTSPDelay1-14,21,39F8toRSPDelayF8toC19DelayC1.5PulseWidthHighorLowC3PulseWidthHighorLowC6PulseWidthHighorLowC2PulseWidthHighorLowC4PulseWidthHighorLowC8PulseWidthHighorLow-10030914972230111521-14,21,391-14,211-3,6-14,21,23,38-2833721711019-45-8-46-10-10-10-10-1010-136323813444-319-3155551010523391758625813370nsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsns* Refer to the Test Conditions on Page 32 for details.

PT0106(09/02)

Ver:0

元器件交易网www.cecb2b.com

Data SheetPT7A4410/4410L

T1/E1/OC3 System Synchronizer

Table 13. Input and Output Timing of 4409L

SymtRWtIRFtR8DtR15DtR2DtF0DtF16DtC15DtC6D1)tC3DtC2DtC4DtC8DtC16DtTSPD1)t1)RSPDDescriptionReferenceInputpulseWidthHighorLowTestConditions*1-3,6-11,39Min100TypMaxUnitsnsReferenceInputRisingorFallingTime8kHzReferenceInputtoF8Delay1.544kHzReferenceInputtoF8Delay2.048kHzReferenceInputtoF8DelayF8toF0DelayF8toF16DelayF8toC1.5DelayF8toC6DelayF8toC3DelayF8toC2DelayF8toC4DelayF8toC8DelayF8toC16DelayF8toTSPDelay1-14,21,39F8toRSPDelayF8toC19DelayC1.5PulseWidthHighorLowC3PulseWidthHighorLowC6PulseWidthHighorLowC2PulseWidthHighorLowC4PulseWidthHighorLowC8PulseWidthHighorLow-10030914972230111521-14,21,391-14,211-3,6-14,21,23,38-2134523211219-47-9-49-11-11-11-11-1010637124813844-319-3244441010523391758625813370nsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnstC19D1)tC15WtC3WtC6W1)tC2WtC4WtC8W* Refer to the Test Conditions on Page 32 for details.

PT0106(09/02)

Ver:0

元器件交易网www.cecb2b.com

Data SheetPT7A4410/4410L

T1/E1/OC3 System Synchronizer

Table 14. Input and Output Timing (Continued)

SymtC16WLtTSPWtRSPWtC19WtF0WLtF8WHtF16WLtORFtStHDescriptionC16PulseWidthLowTSPPulseWidthHighRSPPulseWidthHighC19PulseWidthHighorLowF0PulseWidthLowF8PulseWidthHighF16PulseWidthLowOutputClockandFramePulseRisingorFallingTimeInputControlsSetupTimeInputControlsHoldTime1-14,21,391-14,21TestConditions*Min264784781623011152TypMax3749449536258133709100100Unitsnsnsnsnsnsnsnsnsnsns* Refer to the Test Conditions on Page 32 for details. Figure 17. Input to Output Timing (Normal State, after TCLR or RST)tR8DPRI/SEC8kHztR15DPRI/SEC1.544MHztRWVTtRWVTtR2DPRI/SEC2.048MHzF8tRWVTVTNote: Input to output delay values are valid after a TCLR or RST with no further state changes.PT0106(09/02)

Ver:0

元器件交易网www.cecb2b.com

Data SheetPT7A4410/4410L

T1/E1/OC3 System Synchronizer

Figure 18. Output Timing

tF8WHF8VTtF0WLF0tF0DVTtF16DF16tF16WLtC16WLtC16DVTC16VTtC8WC8tC8WtC8DVTtC4WC4tC4DtC4WVTC2tC2WtC2DVTtC3WC3tC3WtC3DVTtC15WC1.5tC15DVTtC6WC6tC6WtC6DVTtC19WC19tC19DVTtC19W Figure 19. Output Timing

F8C2tRSPDRSPTSPPT0106(09/02)

VTVTVTVTVer:0

tTSPWtTSPDtRSPW25

元器件交易网www.cecb2b.com

Data SheetPT7A4410/4410L

T1/E1/OC3 System Synchronizer

Figure 20. Setup and Hold Timing of Input Controls

F8VTtS tHMS1,2LOS1,2RSELGTiVTIntrinsic Jitter Unfiltered

Table 15. Intrinsic Jitter Unfiltered

SymDescriptionInstrinsicJitteratF8(8kHz)InstrinsicJitteratF0(8kHz)InstrinsicJitteratF16(8kHz)InstrinsicJitteratC1.5(1.544MHz)InstrinsicJitteratC2(2.048MHz)InstrinsicJitteratC3(3.088MHz)InstrinsicJitteratC4(4.096MHz)InstrinsicJitteratC6(6.312MHz)InstrinsicJitteratC8(8.192MHz)InstrinsicJitteratC16(16.384MHz)InstrinsicJitteratC19(19.44MHz)InstrinsicJitteratTSP(8kHz)InstrinsicJitteratRSP(8kHz)TestConditions*MinTypMax0.0002UnitsUIppUIppUIppUIppUIppUIppUIppUIppUIppUIppUIppUIppUIpp1-14,21-24,280.00020.00021-14,21-24,291-14,21-24,301-14,21-24,311-14,21-24,321-14,21-24,411-14,21-24,331-14,21-24,341-14,21-24,421-14,21-24,281-14,21-24,280.0300.0400.0600.0800.1200.1600.3200.2300.00020.0002* Refer to the Test Conditions on Page 32 for details.

PT0106(09/02)

Ver:0

元器件交易网www.cecb2b.com

Data SheetPT7A4410/4410L

T1/E1/OC3 System Synchronizer

C1.5 (1.544MHz) Instrinsic Jitter Filtered

Table 16. C1.5 (1.544MHz) Instrinsic Jitter Filtered

SymDescriptionInstrinsicJitter(4Hzto100kHzFilter)InstrinsicJitter(10Hzto40kHzFilter)1-14,21-24,29InstrinsicJitter(8kHzto40kHzFilter)InstrinsicJitter(10Hzto8kHzFilter)* Refer to the Test Conditions on Page 32 for details.

TestConditions*MinTypMax0.0150.0100.0100.005UnitsUIppUIppUIppUIppC2 (2.048MHz) Instrinsic Jitter Filtered

Table 17. C2 (2.048MHz) Instrinsic Jitter Filtered

SymDescriptionInstrinsicJitter(4Hzto100kHzFilter)InstrinsicJitter(10Hzto40kHzFilter)1-14,21-24,30InstrinsicJitter(8kHzto40kHzFilter)InstrinsicJitter(10Hzto8kHzFilter)* Refer to the Test Conditions on Page 32 for details.

TestConditions*MinTypMax0.0150.0100.0100.005UnitsUIppUIppUIppUIppPT0106(09/02)

Ver:0

元器件交易网www.cecb2b.com

Data SheetPT7A4410/4410L

T1/E1/OC3 System Synchronizer

8kHz Input to 8kHz Output Jitter Transfer

Table 18. 8kHz Input to 8kHz Output Jitter Transfer

SymDescriptionJitterAttenuationfor1Hzwith0.01UIppInputJitterAttenuationfor1Hzwith0.54UIppInputJitterAttenuationfor10Hzwith0.10UIppInputJitterAttenuationfor60Hzwith0.10UIppInputJitterAttenuationfor300Hzwith0.10UIppInputJitterAttenuationfor3600Hzwith0.005UIppInputTestConditions*Min0612284245TypMax6162238UnitsdBdBdBdBdBdB1-3,6,9-14,21,22,24,28,35* Refer to the Test Conditions on Page 32 for details.

1.544MHz Input to 1.544MHz Output Jitter Transfer

Table 19. 1.544MHz Input to 1.544MHz Output Jitter Transfer

SymDescriptionJitterAttenuationfor1Hzwith20UIppInputJitterAttenuationfor1Hzwith104UIppInputJitterAttenuationfor10Hzwith20UIppInputJitterAttenuationfor60Hzwith20UIppInputJitterAttenuationfor300Hzwith20UIppInputJitterAttenuationfor10kHzwith0.3UIppInputJitterAttenuationfor100kHzwith0.3UIppInput1-3,7,9-14,21,22,24,29,35TestConditions*Min061228424545TypMax6162238UnitsdBdBdBdBdBdBdB* Refer to the Test Conditions on Page 32 for details.

PT0106(09/02)

Ver:0

元器件交易网www.cecb2b.com

Data SheetPT7A4410/4410L

T1/E1/OC3 System Synchronizer

2.048MHz Input to 2.048MHz Output Jitter Transfer

Table 20. 2.048MHz Input to 2.048MHz Output Jitter Transfer

SymDescriptionTestConditions*1-3,8,9-14,21,22,24,30,35JitteratOutputfor1Hz3.00UIppInput1-3,8,9-14,21,22,24,30,361-3,8,9-14,21,22,24,30,35JitteratOutputfor3Hz2.33UIppInput1-3,8,9-14,21,22,24,30,361-3,8,9-14,21,22,24,30,35JitteratOutputfor5Hz2.07UIppInput1-3,8,9-14,21,22,24,30,361-3,8,9-14,21,22,24,30,35JitteratOutputfor10Hz1.76UIppInput1-3,8,9-14,21,22,24,30,36JitteratOutputfor100Hz1.50UIppInput1-3,8,9-14,21,22,24,30,351-3,8,9-14,21,22,24,30,361-3,8,9-14,21,22,24,30,351-3,8,9-14,21,22,24,30,361-3,8,9-14,21,22,24,30,351-3,8,9-14,21,22,24,30,360.100.060.050.040.030.040.02UIppUIppUIppUIppUIppUIppUIpp0.100.40UIppUIpp0.100.80UIppUIpp0.091.3UIppUIppMinTypMax2.9UnitsUIppJitteratOutputfor2400Hz1.50UIppInputJitteratOutputfor100kHz0.20UIppInput* Refer to the Test Conditions on Page 32 for details.

PT0106(09/02)

Ver:0

元器件交易网www.cecb2b.com

Data SheetPT7A4410/4410L

T1/E1/OC3 System Synchronizer

8kHz Input Jitter Tolerance

Table 21. 8kHz Input Jitter Tolerance

SymDescriptionJitterTolerancefor1HzInputJitterTolerancefor5HzInputJitterTolerancefor20HzInputJitterTolerancefor300HzInput1-3,6,9-14,21,22,24-26,28JitterTolerancefor400HzInputJitterTolerancefor700HzInputJitterTolerancefor2400HzInputJitterTolerancefor3600HzInput0.150.080.020.01UIppUIppUIppUIppTestConditions*Min0.800.700.600.20TypMaxUnitsUIppUIppUIppUIpp* Refer to the Test Conditions on Page 32 for details.

1.544MHz Input Jitter Tolerance

Table 22. 1.544MHz Input Jitter Tolerance

SymDescriptionJitterTolerancefor1HzInputJitterTolerancefor5HzInputJitterTolerancefor20HzInputJitterTolerancefor300HzInputJitterTolerancefor400HzInputJitterTolerancefor700HzInputJitterTolerancefor2400HzInputJitterTolerancefor10kHzInputJitterTolerancefor100kHzInput1-3,7,9-14,21,22,24-26,29TestConditions*Min150140130352515410.5TypMaxUnitsUIppUIppUIppUIppUIppUIppUIppUIppUIpp* Refer to the Test Conditions on Page 32 for details.

PT0106(09/02)

Ver:0

元器件交易网www.cecb2b.com

Data SheetPT7A4410/4410L

T1/E1/OC3 System Synchronizer

2.048MHz Input Jitter Tolerance

Table 23. 2.048MHz Input Jitter Tolerance

SymDescriptionJitterTolerancefor1HzInputJitterTolerancefor5HzInputJitterTolerancefor20HzInputJitterTolerancefor300HzInputJitterTolerancefor400HzInputJitterTolerancefor700HzInputJitterTolerancefor2400HzInputJitterTolerancefor10kHzInputJitterTolerancefor100kHzInputTestConditions*Min15014013050TypMaxUnitsUIppUIppUIppUIppUIppUIppUIppUIppUIpp1-3,8,9-14,21,22,24-26,304020511* Refer to the Test Conditions on Page 32 for details.OSCi 20MHz Master Clock Input

Table 24. OSCi 20MHz Master Clock Input

SymDescriptionTestConditions*15,18Tolerance16,1917,20DutyCycleRisingTimeFallingTimeMin0-32-10040TypMax0+32+100601010Unitsppmppmppm%nsns* Refer to the Test Conditions on Page 32 for details.

PT0106(09/02)

Ver:0

元器件交易网www.cecb2b.com

Data SheetPT7A4410/4410L

T1/E1/OC3 System Synchronizer

Notes:

1. Voltages are with respect to ground (GND) unless otherwise stated.

2. Supply voltage and operation temperature are as per Recommended Operating Conditions.

3. Timing parameters are as per AC Electrical Characteristics - Voltage Levels for Timing Parameter Measurement.

Test Conditions:

1. PRI reference input selected.2. SEC reference input selected.3. Normal State selected.4. Holdover State selected.5. Free-Run State selected.

6. 8kHz frequency source selected.

7. 1.544MHz frequency source selected.8. 2.048MHz frequency source selected.

9. Master clock input OSCi at 20MHz ±0ppm.10. Master clock input OSCi at 20MHz ±32ppm.11. Master clock input OSCi at 20MHz ±100ppm.12. Selected reference input at ±0ppm.13. Selected reference input at ±32ppm.14. Selected reference input at ±100ppm.15. For Free-Run State of ±0ppm.16. For Free-Run State of ±32ppm.17. For Free-Run State of ±100ppm.18. For capture range of ±230ppm.19. For capture range of ±198ppm.20. For capture range of ±130ppm.21. 25pF capacitive load.

22. OSCi Master Clock Jitter is less than 2ns p-p, or 0.04UI p-p where 1UI p-p = 1/20MHz.

23. Jitter on reference input is less than 7ns p-p.24. Applied jitter is sinusoidal.

25. Minimum applied input jitter magnitude to regain syn- chronization.

26. Loss of synchronization is obtained at slightly higher in- put jitter amplitudes.

27. Within 10ms of the state, reference or input change.28. 1UIpp = 125µs for 8kHz signals.

29. 1UIpp = 648ns for 1.544MHz signals.30. 1UIpp = 488ns for 2.048MHz signals.31. 1UIpp = 324ns for 3.088MHz signals.32. 1UIpp = 244ns for 4.096MHz signals.33. 1UIpp = 122ns for 8.192MHz signals.34. 1UIpp = 61ns for 16.384MHz signals.35. No filter.

36. 40Hz to 100kHz bandpass filter.

37. With respect to reference input signal frequency.38. After a RST or TCLR.39. Master clock duty cycle 40% to 60%.

40. Prior to Holdover State, device was in Normal State and phase locked.

41. 1UIpp = 162ns for 6.312MHz signals.42. 1UIpp = 51ns for 19.44MHz signals.

PT0106(09/02)

Ver:0

元器件交易网www.cecb2b.com

Data SheetPT7A4410/4410L

T1/E1/OC3 System Synchronizer

Mechanical Specifications

Figure 21. 44-pin PLCC

PT0106(09/02)

Ver:0

元器件交易网www.cecb2b.com

Data SheetPT7A4410/4410L

T1/E1/OC3 System Synchronizer

Note

Pericom Technology Inc.Email: support@pti.com.cn

China:Asia Pacific:U.S.A.:

Web-Site: www.pti.com.cn, www.pti-ic.com

No. 20 Building, 3/F, 481 Guiping Road, Shanghai, 200233, ChinaTel: (86)-21-6485 0576Fax: (86)-21-6485 2181

Unit 1517, 15/F, Chevalier Commercial Centre, 8 Wang Hoi Rd, Kowloon Bay, HongkongTel: (852)-2243 3660Fax: (852)- 2243 36672380 Bering Drive, San Jose, California 95131, USATel: (1)-408-435 0800Fax: (1)-408-435 1100

Pericom Technology Incorporation reserves the right to make changes to its products or specifications at any time, without notice, in order to

improve design or performance and to supply the best possible product. Pericom Technology does not assume any responsibility for use of anycircuitry described other than the circuitry embodied in Pericom Technology product. The company makes no representations that circuitrydescribed herein is free from patent infringement or other rights, of Pericom Technology Incorporation.

PT0106(09/02)

Ver:0

因篇幅问题不能全部显示，请点此查看更多更全内容

查看全文

首页

养生问答

疾病百科

养生资讯

女性养生

男性养生

PT7A4410LJ资料