交通灯控制电路设计与仿真

交通灯控制电路设计与仿真

一、 实验目的

1、 了解交通灯的燃灭规律。

2、 了解交通灯控制器的工作原理。

3、 熟悉 VHDL 语言编程，了解实际设计中的优化方案。

二、 实验原理

交通灯的显示有很多方式，如十字路口、丁字路口等，而对于同一个路口又有很多不同的显示要求，比如十字路口，车辆如果只要东西和南北方向通行就很简单，而如果车子可以左右转弯的通行就比较复杂，本实验仅针对最简单的南北和东西直行的情况。 要完成本实验，首先必须了解交通路灯的燃灭规律。本实验需要用到实验箱上交通灯模块中的发光二极管，即红、黄、绿各三个。依人们的交通常规， “红灯停， 绿灯行，黄灯提醒” 。 其交通的燃灭规律为： 初始态是两个路口的红灯全亮，之后，东西路口的绿灯亮，南北路口的红灯亮，东西方向通车，延时一段时间后，东西路口绿灯灭，黄灯开始闪烁。闪烁若干次后，东西路口红灯亮，而同时南北路口的绿灯亮，南北方向开始通车，延时一段时间后，南北路口的绿灯灭，黄灯开始闪烁。闪烁若干次后，再切换到东西路口方向，重复上述过程。

在实验中使用 8 个七段码管中的任意两个数码管显示时间。东西路和南北路的通车时间均设定为 20s。数码管的时间总是显示为 19、18、17……2、1、0、19、18……。在显

示时间小于 3 秒的时候，通车方向的黄灯闪烁。

三、 实验内容

本实验要完成任务就是设计一个简单的交通灯控制器，交通灯显示用实验箱

的交通灯模块和七段码管中的任意两个来显示。系统时钟选择时钟模块的 1KHz

时钟，黄灯闪烁时钟要求为 2Hz，七段码管的时间显示为 1Hz脉冲，即每 1s 中递

减一次，在显示时间小于 3 秒的时候，通车方向的黄灯以 2Hz 的频率闪烁。系统

中用 S1 按键进行复位。

实验箱中用到的数字时钟模块、按键开关、数码管与 FPGA 的接口电路，以及

数字时钟源、按键开关、数码管与 FPGA 的管脚连接在以前的实验中都做了详细说

明，这里不在赘述。交通灯模块原理与 LED 灯模块的电路原理一致，当有高电平输

入时 LED 灯就会被点亮，反之不亮。只是 LED 发出的光有颜色之分。其与 FPGA 的

管脚连接如下表 19-1 所示：

四、 实验步骤

1、 打开 QUARTUSII 软件，新建一个工程。

2、 建完工程之后，再新建一个 VHDL File，打开 VHDL 编辑器对话框。

3、 按照实验原理和自己的想法，在 VHDL 编辑窗口编写 VHDL 程序，用户

可参照光盘中提供的示例程序。

4、 编写完 VHDL 程序后，保存起来。

（1）-jtdkz.vhd

library ieee;

use ieee.std_logic_11.all;

entity jtdkz is

port(clk,sm,sb:in std_logic;

mr,my0,mg0,br,by0,bg0:out std_logic);

end entity jtdkz;

architecture art of jtdkz is

type state_type is(A,B,C,D);

signal state:state_type;

begin

cnt:

process(clk) is

variable s:integer range 0 to 45;

variable clr,en:bit;

begin

if(clk'event and clk='1')then

if clr='0'then s:=0;

elsif en='0' then s:=s;

else s:=s+1;

end if;

case state is

when A=>mr<='0';my0<='0';mg0<='1';br<='1';by0<='0';bg0<='0';

if(sb and sm)='1' then

if s=45 then state<= B;clr:='0';en:='0';

else state<=A;clr:='1';en:='1';

end if;

elsif(sb and(not sm))='1'then state<=B;clr:='0';en:='0';

else state<=A;clr:='1';en:='1';

end if;

when B=>mr<='0';my0<='1';mg0<='0';br<='1';by0<='0';bg0<='0';

if s=5 then state<=C;clr:='0';en:='0';

else state<=B;clr:='1';en:='1';

end if;

when C=>mr<='1';my0<='0';mg0<='0';br<='0';by0<='0';bg0<='1';

if(sb and sm)='1' then

if s=25 then state<= D;clr:='0';en:='0';

else state<=C;clr:='1';en:='1';

end if;

elsif sb='0' then state<=D;clr:='0';en:='0';

else state<=C;clr:='1';en:='1';

end if;

when D=>mr<='1';my0<='0';mg0<='0';br<='0';by0<='1';bg0<='0';

if s=5 then state<=A;clr:='0';en:='0';

else state<=D;clr:='1';en:='1';

end if;

end case;

end if;

end process cnt;

end architecture art;

(2)cskz.vhd

library ieee;

use ieee.std_logic_11.all;

use ieee.std_logic_unsigned.all;

entity cskz is

port(ina:in std_logic;

outa:out std_logic);

end entity cskz;

architecture art of cskz is

begin

process(ina) is

begin

if ina='1' then outa<='1';

else outa<='0';

end if;

end process;

end architecture art;

(3)—cnt45s.vhd

library ieee;

use ieee.std_logic_11.all;

use ieee.std_logic_unsigned.all;

entity cnt45s is

port(sb,clk,en45:in std_logic;

dout45m,dout45b:out std_logic_vector(7 downto 0));

end entity cnt45s;

architecture art of cnt45s is

signal cnt6b:std_logic_vector(5 downto 0);

begin

process(sb,clk,en45)is

begin

if sb='0'then cnt6b<=cnt6b-cnt6b-1;

elsif(clk'event and clk='1')then

if en45='1'then cnt6b<=cnt6b+1;

elsif en45='0' then cnt6b<=cnt6b-cnt6b-1;

end if;

end if;

end process;

process(cnt6b)is

begin

case cnt6b is

when \"000000\"=>dout45m<=\"01000101\";dout45b<=\"01010000\";

when \"000001\"=>dout45m<=\"01000100\";dout45b<=\"01001001\";

when \"000010\"=>dout45m<=\"01000011\";dout45b<=\"01001000\";

when \"000011\"=>dout45m<=\"01000010\";dout45b<=\"01000111\";

when \"000100\"=>dout45m<=\"01000001\";dout45b<=\"01000110\";

when \"000101\"=>dout45m<=\"01000000\";dout45b<=\"01000101\";

when \"000110\"=>dout45m<=\"00111001\";dout45b<=\"01000100\";

when \"000111\"=>dout45m<=\"00111000\";dout45b<=\"01000011\";

when \"001000\"=>dout45m<=\"00110111\";dout45b<=\"01000010\";

when \"001001\"=>dout45m<=\"00110110\";dout45b<=\"01000001\";

when \"001010\"=>dout45m<=\"00110101\";dout45b<=\"01000000\";

when \"001011\"=>dout45m<=\"00110100\";dout45b<=\"01101001\";

when \"001100\"=>dout45m<=\"00110011\";dout45b<=\"00111000\";

when \"001101\"=>dout45m<=\"00110010\";dout45b<=\"00110111\";

when \"001110\"=>dout45m<=\"00110001\";dout45b<=\"00110110\";

when \"001111\"=>dout45m<=\"00110000\";dout45b<=\"00110101\";

when \"010000\"=>dout45m<=\"00101001\";dout45b<=\"00110100\";

when \"010001\"=>dout45m<=\"00101000\";dout45b<=\"00110011\";

when \"010010\"=>dout45m<=\"00100111\";dout45b<=\"00110010\";

when \"010011\"=>dout45m<=\"00100110\";dout45b<=\"00110001\";

when \"010100\"=>dout45m<=\"00100101\";dout45b<=\"00110000\";

when \"010101\"=>dout45m<=\"00100100\";dout45b<=\"00101001\";

when \"010110\"=>dout45m<=\"00100011\";dout45b<=\"00101000\";

when \"010111\"=>dout45m<=\"00100010\";dout45b<=\"00100111\";

when \"011000\"=>dout45m<=\"00100001\";dout45b<=\"00100110\";

when \"011001\"=>dout45m<=\"00100000\";dout45b<=\"00100101\";

when \"011010\"=>dout45m<=\"00011001\";dout45b<=\"00100100\";

when \"011011\"=>dout45m<=\"00011000\";dout45b<=\"00100011\";

when \"011100\"=>dout45m<=\"00010111\";dout45b<=\"00100010\";

when \"011101\"=>dout45m<=\"00010110\";dout45b<=\"00100001\";

when \"011110\"=>dout45m<=\"00010101\";dout45b<=\"00100000\";

when \"011111\"=>dout45m<=\"00010100\";dout45b<=\"00011001\";

when \"100000\"=>dout45m<=\"00010011\";dout45b<=\"00011000\";

when \"100001\"=>dout45m<=\"00010010\";dout45b<=\"00010111\";

when \"100010\"=>dout45m<=\"00010001\";dout45b<=\"00010110\";

when \"100011\"=>dout45m<=\"00010000\";dout45b<=\"00010101\";

when \"100100\"=>dout45m<=\"00001001\";dout45b<=\"00010100\";

when \"100101\"=>dout45m<=\"00001000\";dout45b<=\"00010011\";

when \"100110\"=>dout45m<=\"00000111\";dout45b<=\"00010010\";

when \"100111\"=>dout45m<=\"00000110\";dout45b<=\"00010001\";

when \"101000\"=>dout45m<=\"00000101\";dout45b<=\"00010000\";

when \"101001\"=>dout45m<=\"00000100\";dout45b<=\"00001001\";

when \"101010\"=>dout45m<=\"00000011\";dout45b<=\"00001000\";

when \"101011\"=>dout45m<=\"00000010\";dout45b<=\"00000111\";

when \"101100\"=>dout45m<=\"00000001\";dout45b<=\"00000110\";

when others=>dout45m<=\"00000000\";dout45b<=\"00000000\";

end case;

end process;

end architecture art;

(4)cnt05s.vhd

library ieee;

use ieee.std_logic_11.all;

use ieee.std_logic_unsigned.all;

entity cnt05s is

port(clk,en05m,en05b:in std_logic;

dout5:out std_logic_vector(7 downto 0));

end entity cnt05s;

architecture art of cnt05s is

signal cnt3b:std_logic_vector(2 downto 0);

begin

process(clk,en05m,en05b)is

begin

if(clk'event and clk='1')then

if en05m='1'then cnt3b<=cnt3b+1;

elsif en05b='1'then cnt3b<=cnt3b+1;

elsif en05b='0'then cnt3b<=cnt3b-cnt3b-1;

end if;

end if;

end process;

process(cnt3b)is

begin

case cnt3b is

when \"000\"=>dout5<=\"00000101\";

when \"001\"=>dout5<=\"00000100\";

when \"010\"=>dout5<=\"00000011\";

when \"011\"=>dout5<=\"00000010\";

when \"100\"=>dout5<=\"00000001\";

when others=>dout5<=\"00000000\";

end case;

end process;

end architecture art;

(5)—cnt25s.vhd

library ieee;

use ieee.std_logic_11.all;

use ieee.std_logic_unsigned.all;

entity cnt25s is

port(sb,sm,clk,en25:in std_logic;

dout25m,dout25b:out std_logic_vector(7 downto 0));

end entity cnt25s;

architecture art of cnt25s is

signal cnt5b:std_logic_vector(4 downto 0);

begin

process(sb,sm,clk,en25)is

begin

if sb='0'then cnt5b<=cnt5b-cnt5b-1;

elsif sm='0' then cnt5b<=cnt5b-cnt5b-1;

elsif(clk'event and clk='1') then

if en25='1' then cnt5b<=cnt5b+1;

elsif en25='0' then cnt5b<=cnt5b-cnt5b-1;

end if;

end if;

end process;

process(cnt5b)is

begin

case cnt5b is

when \"00000\"=>dout25b<=\"00100101\";dout25m<=\"00110000\";

when \"00001\"=>dout25b<=\"00100100\";dout25m<=\"00101001\";

when \"00010\"=>dout25b<=\"00100011\";dout25m<=\"00101000\";

when \"00011\"=>dout25b<=\"00100010\";dout25m<=\"00100111\";

when \"00100\"=>dout25b<=\"00100001\";dout25m<=\"00100110\";

when \"00101\"=>dout25b<=\"00100000\";dout25m<=\"00100101\";

when \"00110\"=>dout25b<=\"00011001\";dout25m<=\"00100100\";

when \"00111\"=>dout25b<=\"00011000\";dout25m<=\"00100011\";

when \"01000\"=>dout25b<=\"00010111\";dout25m<=\"00100010\";

when \"01001\"=>dout25b<=\"00010110\";dout25m<=\"00100001\";

when \"01010\"=>dout25b<=\"00010101\";dout25m<=\"00100000\";

when \"01011\"=>dout25b<=\"00010100\";dout25m<=\"00011001\";

when \"01100\"=>dout25b<=\"00010011\";dout25m<=\"00011000\";

when \"01101\"=>dout25b<=\"00010010\";dout25m<=\"00010111\";

when \"01110\"=>dout25b<=\"00010001\";dout25m<=\"00010110\";

when \"01111\"=>dout25b<=\"00010000\";dout25m<=\"00010101\";

when \"10000\"=>dout25b<=\"00001001\";dout25m<=\"00010100\";

when \"10001\"=>dout25b<=\"00001000\";dout25m<=\"00010011\";

when \"10010\"=>dout25b<=\"00000111\";dout25m<=\"00010010\";

when \"10011\"=>dout25b<=\"00000110\";dout25m<=\"00010001\";

when \"10100\"=>dout25b<=\"00000101\";dout25m<=\"00010000\";

when \"10101\"=>dout25b<=\"00000100\";dout25m<=\"00010001\";

when \"10110\"=>dout25b<=\"00000011\";dout25m<=\"00001000\";

when \"10111\"=>dout25b<=\"00000010\";dout25m<=\"00000111\";

when \"11000\"=>dout25b<=\"00000001\";dout25m<=\"00000110\";

when others=>dout25b<=\"00000000\";dout25m<=\"00000000\";

end case;

end process;

end architecture art;

(6)—xskz.vhd

library ieee;

use ieee.std_logic_11.all;

use ieee.std_logic_unsigned.all;

entity xskz is

port(en45,en25,en05m,en05b:in std_logic;

ain45m,ain45b,ain25m,ain25b,ain05:in std_logic_vector(7 downto 0);

doutm,doutb:out std_logic_vector(7 downto 0));

end entity xskz;

architecture art of xskz is

begin

process(en45,en25,en05m,en05b,ain45m,ain45b,ain25m,ain25b,ain05)is

begin

if en45='1'then doutm<=ain45m(7 downto 0);doutb<=ain45b(7 downto 0);

elsif en05m='1'then doutm<=ain05(7 downto 0);doutb<=ain05(7 downto 0);

elsif en25='1'then doutm<=ain25m(7 downto 0);doutb<=ain25b(7 downto 0);

elsif en05b='1'then doutm<=ain05(7 downto 0);doutb<=ain05(7 downto 0);

end if;

end process;

end architecture art;

(7)—ymq.vhd

library ieee;

use ieee.std_logic_11.all;

use ieee.std_logic_unsigned.all;

entity ymq is

port(clk:in std_logic;

ain41,ain42,ain43,ain44:in std_logic_vector(3 downto 0);

del:out std_logic_vector(2 downto 0);

dout7:out std_logic_vector(6 downto 0));

end entity ymq;

architecture art of ymq is

signal ain4: std_logic_vector(3 downto 0);

signal cnt: std_logic_vector(2 downto 0);

begin

process(clk)

begin

if clk'event and clk='1' then

if cnt=\"011\" then

cnt<=\"000\";

else

cnt<=cnt+1;

end if;

end if;

end process;

process(cnt,ain41,ain42,ain43,ain44)

begin

case cnt is

when \"000\" => ain4<=ain41; del<=\"111\";

when \"001\" => ain4<=ain42; del<=\"110\";

when \"010\" => ain4<=ain43; del<=\"101\";

when \"011\" => ain4<=ain44; del<=\"100\";

when \"100\" => ain4<=ain41; del<=\"000\";

when \"101\" => ain4<=ain41; del<=\"000\";

when \"110\" => ain4<=ain41; del<=\"000\";

when \"111\" => ain4<=ain41; del<=\"000\";

end case;

end process;

process(ain4)is

begin

case ain4 is

when \"0000\"=>dout7<=\"0111111\";

when \"0001\"=>dout7<=\"0000110\";

when \"0010\"=>dout7<=\"1011011\";

when \"0011\"=>dout7<=\"1001111\";

when \"0100\"=>dout7<=\"1100110\";

when \"0101\"=>dout7<=\"1101101\";

when \"0110\"=>dout7<=\"1111101\";

when \"0111\"=>dout7<=\"0000111\";

when \"1000\"=>dout7<=\"1111111\";

when \"1001\"=>dout7<=\"1101111\";

when others=>dout7<=\"0000000\";

end case;

end process;

end architecture art;

(8)—jtkzq.vhd

library ieee;

use ieee.std_logic_11.all;

entity jtkzq is

port(

clk,sm,sb:in std_logic;

mr,mg,my,by,br,bg:out std_logic;

del1:out std_logic_vector(2 downto 0);

dout:out std_logic_vector(6 downto 0));

end entity jtkzq;

architecture art of jtkzq is

component div_clk is

port(clk : in std_logic;

clk1:out std_logic);

end component div_clk;

component jtdkz is

port(clk,sm,sb:in std_logic;

mr,my0,mg0,br,by0,bg0:out std_logic);

end component jtdkz;

component cskz is

port(

ina:in std_logic;

outa:out std_logic);

end component cskz;

component cnt45s is

port(sb,clk,en45:in std_logic;

dout45m,dout45b:out std_logic_vector(7 downto 0));

end component cnt45s;

component cnt05s is

port(clk,en05m,en05b:in std_logic;

dout5:out std_logic_vector(7 downto 0));

end component cnt05s;

component cnt25s is

port(sb,sm,clk,en25:in std_logic;

dout25m,dout25b:out std_logic_vector(7 downto 0));

end component cnt25s;

component xskz is

port(en45,en25,en05m,en05b:in std_logic;

ain45m,ain45b,ain25m,ain25b,ain05:in std_logic_vector(7 downto 0);

doutm,doutb:out std_logic_vector(7 downto 0));

end component xskz;

component ymq is

port(clk:in std_logic;

ain41,ain42,ain43,ain44:in std_logic_vector(3 downto 0);

del:out std_logic_vector(2 downto 0);

dout7:out std_logic_vector(6 downto 0));

end component ymq;

signal clk11:std_logic;

signal en1,en2,en3,en4:std_logic;

signal s45m,s45b,s05,s25m,s25b:std_logic_vector(7 downto 0);

signal ym1,ym2,ym3,ym4:std_logic_vector(3 downto 0);

begin

u1:div_clk port map(clk=>clk,clk1=>clk11);

u2:jtdkz port

map(clk=>clk11,sm=>sm,sb=>sb,mr=>mr,my0=>en2,mg0=>en1,br=>br,by0=>en4,bg0=>en3);

u3:cskz port map(ina=>en1,outa=>mg);

u4:cskz port map(ina=>en2,outa=>my);

u5:cskz port map(ina=>en3,outa=>bg);

u6:cskz port map(ina=>en4,outa=>by);

u7:cnt45s port

map(clk=>clk11,sb=>sb,en45=>en1,dout45m=>s45m,dout45b=>s45b);

u8:cnt05s port map(clk=>clk11,en05m=>en2,dout5=>s05,en05b=>en4);

u9:cnt25s port

map(clk=>clk11,sm=>sm,sb=>sb,en25=>en3,dout25m=>s25m,dout25b=>s25b);

u10:xskz port

map(en45=>en1,en05m=>en2,en25=>en3,en05b=>en4,ain45m=>s45m,ain45b=>s45b,ain25m=>s25m,ain25b=>s25b,ain05=>s05,doutm(3 downto

0)=>ym1,doutm(7 downto 4)=>ym2,doutb(3 downto 0)=>ym3,doutb(7 downto 4)=>ym4);

u11:ymq port

map(clk=>clk,ain41=>ym1,ain42=>ym2,ain43=>ym3,ain44=>ym4,del=>del1,dout7=>dout);

end architecture art;

(9)—div_clk.vhd

library ieee;

use ieee.std_logic_11.all;

use ieee.std_logic_unsigned.all;

entity div_clk is

port(clk : in std_logic;

clk1:out std_logic);

end div_clk;

architecture behav of div_clk is

signal cnt:integer range 1000 downto 0;

begin

process(clk)

begin

if clk'event and clk='1' then

if cnt=999 then

cnt<=0;

else

cnt<=cnt+1;

end if;

if cnt<500 then

clk1<='0';

else

clk1<='1';

end if;

end if;

end process;

end behav;

5 引脚分配

6 实验现象

当主、支道均有车时，两者交替允许通行，主干道每次放行45s，支干道每次放行25s，在每次由亮绿灯变成亮红灯的转换过程中，要亮5s的黄灯作为过度，并进行减计时显示。